# US 10,374,032 B2 · Field-effect semiconductor device having N and P-doped pillar regions

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- Number: US 10,374,032 B2
- Document ID: US10374032B2
- Status: Granted
- Kind: B2
- Application number: 15/944,948
- Filed: 2018-04-04
- Published: 2018-10-11
- Granted: 2019-08-06
- Earliest claimed: 2018-04-04
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Hans Weber; Christian Fachmann; Gabor Mezoesi; Andreas Riegler
- Web page: https://patentgrep.com/patent/US10374032B2

## CPC

- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/411: {Insulated-gate bipolar transistors [IGBT]}
- H10D 12/421: {on insulating layers or insulating substrates, e.g. thin-film IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 12/491: {having both emitter contacts and collector contacts in the same substrate side}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/664: {Inverted VDMOS transistors, i.e. source-down VDMOS transistors}
- H10D 30/665: {having edge termination structures}
- H10D 30/667: {having substrates comprising insulating layers, e.g. SOI-VDMOS transistors}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/01: Manufacture or treatment
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H10P 32/1406: {by ion implantation}
- H10P 32/171: {being group IV material}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/465: {Bumps or wires}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 90/811: {Multiple chips on leadframes}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor body having first and second opposite sides, a drift region, a body layer at the second side, and a field-stop region in Ohmic connection with the body layer. A source metallization at the second side is in Ohmic connection with the body layer. A drain metallization at the first side is in Ohmic connection with the drift region. A gate electrode at the second side is electrically insulated from the semiconductor body to define an operable switchable channel region in the body layer. A through contact structure extends at least between the first and second sides, and includes a conductive region in Ohmic connection with the gate electrode and a dielectric layer. In a normal projection onto a horizontal plane substantially parallel to the first side, the field-stop region surrounds at least one of the drift region and the gate electrode.

## Claims

### Claim 1

A field-effect semiconductor device, comprising:
a semiconductor body comprising:
a first side;
a second side opposite the first side;
an n-type drift region;
a p-type body layer forming a pn-junction with the drift region and arranged at the second side; and
a p-type field-stop region in Ohmic connection with the body layer;
a source metallization arranged on the second side and in Ohmic connection with the body layer;
a drain metallization arranged on the first side and in Ohmic connection with the drift region;
a gate electrode arranged adjacent to the second side and electrically insulated from the semiconductor body to define an operable switchable channel region in the body layer for providing an Ohmic connection between the source metallization and the drift region;
a first through contact structure extending at least between the first side and the second side, and comprising a conductive region in Ohmic connection with the gate electrode, and a dielectric layer electrically insulating the conductive region from the semiconductor body; and
a gate metallization arranged on the first side and in Ohmic connection with the conductive region,
wherein in a normal projection onto a horizontal plane substantially parallel to the first side, the field-stop region surrounds at least one of the drift region and the gate electrode.

### Claim 2 (depends on 1)

The field-effect semiconductor device of claim 1, wherein the field-effect semiconductor device has a rated breakdown voltage of at least 100 V, wherein the field-effect semiconductor device is a charge-compensation semiconductor device, wherein the semiconductor body comprises compensation regions each of which adjoins the body layer and forms a respective pn-junction with the drift region, wherein the field-stop region surrounds the compensation regions in the normal projection onto the horizontal plane, and/or wherein the compensation regions form a lattice.

### Claim 3 (depends on 1)

The field-effect semiconductor device of claim 1, wherein the field-stop region has a lower doping concentration than the body layer, and/or wherein the field-stop region has, in a vertical direction perpendicular to the horizontal plane, a vertical extension which is at least about 70% of a distance between the first side and the second side.

### Claim 4 (depends on 1)

The field-effect semiconductor device of claim 1, wherein the first through contact structure extends through the field-stop region, wherein the first through contact structure adjoins the field-stop region, wherein at least a portion of the field-stop region is, in the normal projection onto the horizontal plane, arranged between the first through contact structure and at least one of the drift region and the gate electrode, wherein the first through contact structure does not surround the gate electrode in the normal projection onto the horizontal plane, and/or wherein the conductive region extends through a dielectric layer arranged on the first side.

### Claim 5 (depends on 1)

The field-effect semiconductor device of claim 1, wherein the gate metallization comprises at least one of a gate pad portion and a gate field plate portion arranged between the gate pad portion and the drain metallization, and/or wherein the field-effect semiconductor device further comprises at least one of a source pad arranged on the first side and in Ohmic connection with the source metallization, and a source field plate arranged on the first side, in Ohmic connection with the source metallization, and arranged between the source pad and the drain metallization.

### Claim 6 (depends on 1)

The field-effect semiconductor device of claim 1, further comprising at least one of:
a second through contact structure extending from the first side to the source metallization and comprising a conductive region in Ohmic connection with the source metallization and a dielectric layer separating the conductive region from the semiconductor body;
an n-type contact region arranged, in a vertical cross-section perpendicular to the first side, between a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first side and the p-type field-stop region, and in Ohmic connection with the source metallization or the gate metallization; and
an n-type edge region arranged in the vertical cross-section between the lateral edge and the p-type field-stop region.

### Claim 7 (depends on 1)

The field-effect semiconductor device of claim 1, further comprising an n-type field-stop region having a higher doping concentration than the drift region and arranged between the drift region and the drain metallization.

### Claim 8 (depends on 1)

The field-effect semiconductor device of claim 1, further comprising a p-type JTE-region having a lower doping concentration than the field-stop region, wherein the JTE-region extends from the field-stop region to the first side, wherein the JTE-region extends from the drift region to the first side, and/or wherein the JTE-region at least substantially surrounds the n-type field-stop region in the normal projection on the horizontal plane.

### Claim 9

A field-effect semiconductor device, comprising:
a semiconductor body comprising:
a first side;
a second side opposite the first side;
a semiconductor structure of a second conductivity type at least substantially extending from the first side to the second side; and
a drift region of a first conductivity type arranged, in a vertical cross-section substantially perpendicular to the first side, between two portions of the semiconductor structure;
a first metallization arranged on the second side and in Ohmic connection with the semiconductor structure;
a second metallization arranged on the first side and in Ohmic connection with the drift region;
a plurality of gate electrodes arranged adjacent to the second side, overlapping with the drift region in a normal projection onto a horizontal plane substantially parallel to the first side, and electrically insulated from the semiconductor body;
a first through contact structure extending at least between the first side and the second side, and comprising a conductive region in Ohmic connection with the gate electrodes, and a dielectric layer electrically insulating the conductive region from the semiconductor body so that at least a portion of the semiconductor structure is, in the normal projection onto the horizontal plane, arranged between the first through contact structure and the gate electrodes; and
a gate pad arranged on the first side and in Ohmic connection with the conductive region.

### Claim 10 (depends on 9)

The field-effect semiconductor device of claim 9, wherein the field-effect semiconductor device has a rated breakdown voltage of at least 100 V, wherein the field-effect semiconductor device is a charge-compensation semiconductor device, and/or wherein the semiconductor body comprises a plurality of compensation regions which are spaced apart from each other, form respective pn-junctions with the drift region, form a lattice, and/or are surrounded by the semiconductor structure in the normal projection onto the horizontal plane.

### Claim 11 (depends on 9)

The field-effect semiconductor device of claim 9, wherein the semiconductor structure comprises at least one of:
a field-stop region of the second conductivity type having in a vertical direction substantially perpendicular to the first side an extension which is at least about three quarters of a distance between the first side and the second side;
a body layer of the second conductivity type having a higher doping concentration than the field-stop region, arranged at the second side and forming a pn-junction with the drift region; and
a JTE-region of the second conductivity type having a different doping concentration than the field-stop region.

### Claim 12 (depends on 11)

The field-effect semiconductor device of claim 11, wherein the field-stop region surrounds the drift region in the normal projection on the horizontal plane, wherein the field-stop region extends from the body layer at least close to the first side, wherein the field-stop region has a lower doping concentration than the body layer, and/or wherein the field-stop region has, in a vertical direction perpendicular to the horizontal plane, a vertical extension which is at least about 70% of a distance between the first side and the second side, typically at least about 75% of the distance between the first side and the second side.

### Claim 13 (depends on 9)

The field-effect semiconductor device of claim 9, further comprising a dielectric layer arranged on the first side and comprising a first opening which overlaps with the drift region and a second opening which overlaps with the conductive region of the first through contact structure in the normal projection onto the horizontal plane.

### Claim 14 (depends on 9)

The field-effect semiconductor device of claim 9, further comprising a source layer forming a further pn-junction with the body layer and arranged at the second side.