# US 10,374,031 B2 · Semiconductor device and manufacturing method of semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,031 B2 - Document ID: US10374031B2 - Status: Granted - Kind: B2 - Application number: 15/836,931 - Filed: 2017-12-11 - Published: 2018-06-21 - Granted: 2019-08-06 - Earliest claimed: 2016-12-21 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Katsunori Ueno; Shinya Takashima; Masaharu Edo - Web page: https://patentgrep.com/patent/US10374031B2 ## CPC - H10D 62/109: {Reduced surface field [RESURF] PN junction structures} - H10D 30/0295: {using recessing of the source electrodes} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 62/157: {Impurity concentrations or distributions} - H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 62/405: {Orientations of crystalline planes} - H10D 62/8325: {Silicon carbide} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D 64/0116: {to Group III-V semiconductors} - H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10P 30/2042: {into crystalline silicon carbide} - H10P 30/21: {of electrically active species} - H10P 30/218: {characterised by the implantation in a compound semiconductor of both electrically active and inactive species in the same semiconductor region to be doped n-type or p-type} - H10P 30/28: characterised by an annealing step, e.g. for activation of dopants - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Provided is a semiconductor device including at least two isolation trench portions; a mesa region that is provided between the at least two isolation trench portions and includes a source region having a first conduction type, a base region having a second conduction type and at least a portion thereof provided below the source region, and a gate trench portion; and a contact layer that is an epitaxial layer provided at least in contact with side portions of the mesa region and bottom portions of the isolation trench portions positioned lower than the gate trench portion, and having a second-conduction-type impurity concentration higher than that of the base region, wherein the same impurities as in the contact layer are present in the source region, or the contact layer is provided higher than the source region. ## Claims ### Claim 1 A semiconductor device comprising: at least two isolation trench portions; a mesa region that is provided between the at least two isolation trench portions and includes a source region having a first conduction type, a base region having a second conduction type and at least a portion thereof provided below the source region, and a gate trench portion; and a contact layer that is an epitaxial layer provided at least in contact with side portions of the mesa region and bottom portions of the isolation trench portions positioned lower than the gate trench portion, and having a second-conduction-type impurity concentration higher than that of the base region, wherein the same impurities as in the contact layer are present in the source region, or the contact layer is provided higher than the source region, the mesa region and the contact layer are formed of a GaN-based semiconductor material, the contact layer has an opening on the source region, the contact layer contacts a top portion of the mesa region, and in a top view of the semiconductor device, a position of an end portion of the opening of the contact layer matches a position of a side end portion of the source region. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the same impurities as in the contact layer are present in the source region, and the second-conduction-type impurity concentration in the source region and the second-conduction-type impurity concentration in the contact layer provided in contact with the bottom portions of the isolation trench portions are the same. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the base region has a tail region in which the impurity concentration of impurities with a first conduction type, which is the same conduction type as the impurities of the source region, gradually decreases in a depth direction of the gate trench portion. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the contact layer is provided on the source region, and the semiconductor device further comprises a source electrode having at least a portion thereof provided on the contact layer that is provided on the mesa region, and penetrating through the contact layer to contact the source region. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the second-conduction-type impurity concentration of the contact layer provided on the side portions of the mesa region and the second-conduction-type impurity concentration of the contact layer provided in contact with the bottom portions of the isolation trench portions are the same. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the second-conduction-type impurity concentration of the contact layer provided on the side portions of the mesa region is higher than the second-conduction-type impurity concentration of the contact layer provided in contact with the bottom portions of the isolation trench portions. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein in a top view of the semiconductor device, an end portion of the opening of the contact layer is positioned on a side end portion of the source region. ### Claim 8 A method of manufacturing a semiconductor device, comprising: epitaxially forming a base region with a second conduction type on a drift region with a first conduction type; forming a mesa region between at least two isolation trench portions, by partially etching the drift region and the base region; epitaxially forming a contact layer that contacts a top portion of the mesa region, side portions of the mesa region, and bottom portions of the isolation trench portions, has an opening on the source region, has a position of an end portion of the opening that matches a position of a side end portion of the source region in a top view of the semiconductor device, and has a second-conduction-type impurity concentration that is higher than that of the base region; and forming a gate trench portion. ### Claim 9 (depends on 8) The method of manufacturing the semiconductor device according to claim 8, further comprising: ion-implanting impurities with a first conduction type in a predetermined region of the contact layer provided on the top portion of the mesa region, after the epitaxially forming the contact layer and before the forming the gate trench portion. ### Claim 10 (depends on 8) The method of manufacturing the semiconductor device according to claim 8, further comprising: epitaxially forming a source region with a first conduction type on the base region, after the epitaxially forming the base region and before the forming the mesa region. ### Claim 11 A method of manufacturing a semiconductor device, comprising: epitaxially forming a base region with a second conduction type on a drift region with a first conduction type; forming a mesa region between at least two isolation trench portions, by partially etching the drift region and the base region; epitaxially forming a contact layer that contacts a top portion of the mesa region, side portions of the mesa region, and bottom portions of the isolation trench portions, and has a second-conduction-type impurity concentration that is higher than that of the base region; and forming a gate trench portion, wherein the epitaxially forming the contact layer is performed after the forming the mesa region and before the forming the gate trench portion, and the method of manufacturing the semiconductor device further comprises: thermally treating the contact layer, after the epitaxially forming the contact layer and before the forming the gate trench portion; forming an opening in the contact layer, after the thermally treating the contact layer and before the forming the gate trench portion; and ion-implanting impurities with a first conduction type in the base region via at least the opening, after the forming the opening in the contact layer and before the forming the gate trench portion. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the base region is provided covering corner portions positioned at bottom ends of side portions of the gate trench portion in contact with the base region. ### Claim 13 (depends on 8) The method of manufacturing the semiconductor device according to claim 8, wherein the gate trench portion is formed into the base region of the mesa region to a depth such that the base region is provided covering corner portions positioned at bottom ends of side portions of the gate trench portion in contact with the base region.