# US 10,374,029 B2 · Semiconductor device resistor structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,029 B2 - Document ID: US10374029B2 - Status: Granted - Kind: B2 - Application number: 15/848,324 - Filed: 2017-12-20 - Published: 2018-05-03 - Granted: 2019-08-06 - Earliest claimed: 2016-09-21 - Assignees: GLOBAL FOUNDRIES Inc. - Applicants: Globalfoundries Inc. - Inventors: Hui Zang; Josef S. Watts; Shesh M. Pandey - Web page: https://patentgrep.com/patent/US10374029B2 ## CPC - H10D 1/47: Resistors having no potential barriers - H10D 84/817: {Combinations of field-effect devices and resistors only} - H10P 14/3411: {Silicon, silicon germanium or germanium} - H10P 14/3444: {P-type} - H10P 14/3456: {Polycrystalline} - H10P 14/416: {of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers} - H10P 14/69215: {the material being a silicon oxide, e.g. SiO2} - H10P 14/69392: {the material containing hafnium, e.g. HfO2} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material. ## Claims ### Claim 1 A method of making a semiconductor device resistor structure, the method comprising: providing a first semiconductor layer including a first semiconductor material; depositing a support dielectric material on the first semiconductor layer to form a support dielectric layer on a surface of the first semiconductor layer; forming a plurality of cavities in the support dielectric layer, each cavity extending from a surface of the support dielectric layer to the surface of the first semiconductor layer; forming a well region in the first semiconductor layer by doping the first semiconductor layer to form at least one doped region, the plurality of cavities including at least one resistor cavity over the well region and at least two gate cavities outside of the well region; depositing a resistor dielectric layer on at least the surface of the first semiconductor layer exposed in the plurality of cavities; forming a resistor body in each resistor cavity and on the resistor dielectric layer, the forming of the resistor body in each resistor cavity including depositing a resistive material in each resistor cavity, the depositing of the resistive material including filling the at least two gate cavities with the resistive material; removing the resistive material from the at least two gate cavities; and depositing a gate material at least in the gate cavities. ### Claim 2 (depends on 1) The method of claim 1, wherein the depositing of the resistor dielectric layer includes depositing a gate dielectric material on at least the surface of the well region exposed in the at least one resistor cavity. ### Claim 3 (depends on 1) The method of claim 1, wherein the depositing of the resistor dielectric layer includes depositing at least one of silicon dioxide (SiO2) or hafnium oxide (HfO2) on at least the surface of the well region exposed in the at least one resistor cavity. ### Claim 4 (depends on 1) The method of claim 1, wherein the first semiconductor material includes polysilicon, and the forming of the well region in the first semiconductor layer by doping of the first semiconductor layer to form the at least one doped region includes: implanting a first dopant at a first concentration at a first distance from the surface of the first semiconductor layer and implanting the first dopant at a second concentration at a second distance from the surface of the first semiconductor layer that is greater than the first distance, the first concentration being higher than the second concentration. ### Claim 5 (depends on 4) The method of claim 4, wherein the first semiconductor layer includes silicon and the first dopant includes a P-type dopant. ### Claim 6 A method of making a semiconductor device resistor structure, the method comprising: providing a first semiconductor layer including a first semiconductor material; depositing a support dielectric material on the first semiconductor layer to form a support dielectric layer on a surface of the first semiconductor layer; forming a plurality of cavities in the support dielectric layer, each cavity extending from a surface of the support dielectric layer to the surface of the first semiconductor layer; forming a well region in the first semiconductor layer by doping the first semiconductor layer to form at least one doped region, the plurality of cavities including at least one resistor cavity over the well region; depositing a resistor dielectric layer on at least the surface of the first semiconductor layer exposed in the plurality of cavities; forming gate bodies by depositing a gate material in the plurality of cavities, the depositing of the gate material including filling the at least one resistor cavity with the gate material; and forming a resistor body in each resistor cavity and on the resistor dielectric layer, the forming of the resistor body in each resistor cavity including removing the gate material from the at least one resistor cavity and depositing a resistive material in the at least one resistor cavity. ### Claim 7 (depends on 6) The method of claim 6, wherein the depositing of the resistor dielectric layer includes depositing a gate dielectric material on at least the surface of the well region exposed in the at least one resistor cavity. ### Claim 8 (depends on 6) The method of claim 6, wherein the depositing of the resistor dielectric layer includes depositing at least one of silicon dioxide (SiO2) or hafnium oxide (HfO2) on at least the surface of the well region exposed in the at least one resistor cavity. ### Claim 9 (depends on 6) The method of claim 6, wherein the first semiconductor material includes polysilicon, and the forming of the well region in the first semiconductor layer by doping of the first semiconductor layer to form the at least one doped region includes: implanting a first dopant at a first concentration at a first distance from the surface of the first semiconductor layer and implanting the first dopant at a second concentration at a second distance from the surface of the first semiconductor layer that is greater than the first distance, the first concentration being higher than the second concentration. ### Claim 10 (depends on 9) The method of claim 9, wherein the first semiconductor layer includes silicon and the first dopant includes a P-type dopant. ### Claim 11 A method of making a semiconductor device resistor structure, the method comprising: providing a first semiconductor layer including a first semiconductor material; depositing a support dielectric material on the first semiconductor layer to form a support dielectric layer on a surface of the first semiconductor layer; forming a plurality of cavities in the support dielectric layer, each cavity extending from a surface of the support dielectric layer to the surface of the first semiconductor layer; forming a well region in the first semiconductor layer by doping the first semiconductor layer to form at least one doped region, the plurality of cavities including at least one resistor cavity over the well region, the forming of the well region by doping including implanting a first dopant at a first concentration at a first distance from the surface of the first semiconductor layer and implanting the first dopant at a second concentration at a second distance from the surface of the first semiconductor layer that is greater than the first distance, the first concentration being higher than the second concentration; depositing a resistor dielectric layer on at least the surface of the first semiconductor layer exposed in the plurality of cavities; and forming a resistor body in each resistor cavity and on the resistor dielectric layer. ### Claim 12 (depends on 11) The method of claim 11, wherein the plurality of cavities includes at least two gate cavities outside of the well region; wherein the forming of the resistor body in each resistor cavity includes depositing a resistive material in each resistor cavity, the depositing of the resistive material including filling the at least two gate cavities with the resistive material; and wherein the method further comprises: removing the resistive material from the at least two gate cavities; and depositing a gate material at least in the gate cavities. ### Claim 13 (depends on 11) The method of claim 11, further comprising forming gate bodies by depositing a gate material in the plurality of cavities, the depositing of the gate material including filling the at least one resistor cavity with the gate material; and wherein the forming of the resistor body in each resistor cavity includes: removing the gate material from the at least one resistor cavity, and depositing a resistive material in the at least one resistor cavity. ### Claim 14 (depends on 11) The method of claim 11, wherein the depositing of the resistor dielectric layer includes depositing a gate dielectric material on at least the surface of the well region exposed in the at least one resistor cavity. ### Claim 15 (depends on 11) The method of claim 11, wherein the depositing of the resistor dielectric layer includes depositing at least one of silicon dioxide (SiO2) or hafnium oxide (HfO2) on at least the surface of the well region exposed in the at least one resistor cavity. ### Claim 16 (depends on 11) The method of claim 11, wherein the first semiconductor layer includes silicon and the first dopant includes a P-type dopant.