# US 10,374,025 B2 · Thin film transistor array

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- Number: US 10,374,025 B2
- Document ID: US10374025B2
- Status: Granted
- Kind: B2
- Application number: 14/701,145
- Filed: 2015-04-30
- Published: 2015-08-20
- Granted: 2019-08-06
- Earliest claimed: 2012-10-31
- Assignees: Toppan Printing Co., Ltd.
- Applicants: Toppan Printing Co., Ltd.
- Inventors: Ryohei Matsubara
- Web page: https://patentgrep.com/patent/US10374025B2

## CPC

- H10K 59/125: including organic TFTs [OTFT]
- H10D 1/68: Capacitors having no potential barriers
- H10K 10/466: {Lateral bottom-gate IGFETs comprising only a single gate}
- H10K 10/484: {characterised by the channel regions}
- H10K 19/10: comprising field-effect transistors
- H10K 59/1213: {the pixel elements being TFTs}
- H10K 59/1216: {the pixel elements being capacitors}
- H10K 59/123: Connection of the pixel electrodes to the thin film transistors [TFT]
- H10K 59/131: Interconnections, e.g. wiring lines or terminals
- H10K 77/10: Substrates, e.g. flexible substrates
- H10K 77/111: {Flexible substrates}
- H10K 71/135: {using ink-jet printing}
- H10K 71/611: {using printing deposition, e.g. ink jet printing}
- H10K 85/40: Organosilicon compounds, e.g. TIPS pentacene
- Y02E 10/549: Organic PV cells
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION

## Abstract

A thin film transistor array includes thin film transistors each including a gate electrode formed on an insulation substrate, a source electrode and a drain electrode formed on the gate electrode via a gate insulation film and a semiconductor layer formed on a portion of the gate electrode surrounded by at least the source electrode and the drain electrode; capacitors each including a capacitor electrode formed on the insulation substrate and a pixel electrode which is formed on the capacitor electrode via the gate insulation film and connected to the drain electrode, the capacitors and the thin film transistors being positioned in a matrix along a first direction and a second direction perpendicular to the first direction; and connection lines that connect semiconductor layers of the thin film transistors positioned in the first direction. The connection lines each have a width smaller than a width of the semiconductor layer.

## Claims

### Claim 1

A thin film transistor array, comprising:
a plurality of thin film transistors each including a gate electrode formed on an insulation substrate, a source electrode and a drain electrode formed on the gate electrode via a gate insulation film and a semiconductor layer formed on a portion of the gate electrode surrounded by at least the source electrode and the drain electrode;
a plurality of capacitors each including a capacitor electrode formed on the insulation substrate and a pixel electrode which is formed on the capacitor electrode via the gate insulation film and connected to the drain electrode, the capacitors and the thin film transistors being positioned in a plane along a first direction and a second direction perpendicular to the first direction;
a plurality of source wirings that extend in the first direction and connect source electrodes of the thin film transistors positioned in the first direction; and
a plurality of semiconductor layer connection lines that at least partially overlap the plurality of source wirings along an entirety of a length of the plurality of source wirings in the first direction, the plurality of semiconductor layer connection lines comprising a semiconductor material and extending continuously in the first direction together with the plurality of source wirings, with which the plurality of semiconductor layer connection lines at least partially overlap, to directly connect to the semiconductor layers included in different groups of the thin film transistors positioned in the first direction in channel regions, wherein
a width of the semiconductor layer connection lines, which at least partially overlap the plurality of source wirings along the entirety of the length of the plurality of source wirings in the first direction, in non-channel regions is smaller than a width of the semiconductor layer connection lines with the semiconductor layers of the thin film transistors in the channel regions.

### Claim 2 (depends on 1)

The thin film transistor according to claim 1, further comprising:
a plurality of gate wirings that connect gate electrodes of the thin film transistors positioned in the second direction; and
a plurality of capacitor wirings that connect capacitor electrodes of the capacitors positioned in the second direction.

### Claim 3 (depends on 2)

The thin film transistor according to claim 2, wherein the semiconductor layers and the semiconductor layer connection lines are each formed by an organic semiconductor.

### Claim 4 (depends on 3)

The thin film transistor according to claim 3, wherein the pixel electrode is overlapped with neither the semiconductor layer nor the semiconductor layer connection line.

### Claim 5 (depends on 3)

The thin film transistor array according to claim 3, wherein the source electrode has at least one convex portion extending to the second direction from the source wiring, the convex portion is formed on an outer side of the drain electrode at least in a portion where the semiconductor layer is formed, and the convex portion has an end portion which is formed on the outer side of the drain electrode and is not covered by the semiconductor layer.

### Claim 6 (depends on 5)

The thin film transistor array according to claim 5, wherein the insulation substrate is a flexible substrate.

### Claim 7 (depends on 3)

The thin film transistor array according to claim 3, wherein the source electrode is a concave portion formed in the source wiring, and the semiconductor layer connection line has a portion where the source wiring and the semiconductor layer connection line are not overlapped on a side where the concave portion is formed.

### Claim 8 (depends on 3)

The thin film transistor array according to claim 3, wherein the insulation substrate is a flexible substrate.

### Claim 9 (depends on 2)

The thin film transistor according to claim 2, wherein the pixel electrode is overlapped with neither the semiconductor layer nor the semiconductor layer connection line.

### Claim 10 (depends on 9)

The thin film transistor array according to claim 9, wherein the source electrode has at least one convex portion extending to the second direction from the source wiring, the convex portion is formed on an outer side of the chain electrode at least in a portion where the semiconductor layer is formed, and the convex portion has an end portion which is formed on the outer side of the drain electrode and is not covered by the semiconductor layer.

### Claim 11 (depends on 9)

The thin film transistor array according to claim 9, wherein the source electrode is a concave portion formed in the source wiring, and the semiconductor layer connection line has a portion where the source wiring and the semiconductor layer connection line are not overlapped on a side where the concave portion is formed.

### Claim 12 (depends on 9)

The thin film transistor array according to claim 9, wherein the insulation substrate is a flexible substrate.

### Claim 13 (depends on 2)

The thin film transistor array according to claim 2, wherein the source electrode has at least one convex portion extending to the second direction from the source wiring, the convex portion is formed on an outer side of the drain electrode at least in a portion where the semiconductor layer is formed, and the convex portion has an end portion which is formed on the outer side of the drain electrode and is not covered by the semiconductor layer.

### Claim 14 (depends on 13)

The thin film transistor array according to claim 13, wherein the insulation substrate is a flexible substrate.

### Claim 15 (depends on 2)

The thin film transistor array according to claim 2, wherein the source electrode is a concave portion formed in the source wiring, and the semiconductor layer connection line has a portion where the source wiring and the semiconductor layer connection line are not overlapped on a side where the concave portion is formed.

### Claim 16 (depends on 2)

The thin film transistor array according to claim 2, wherein the insulation substrate is a flexible substrate.

### Claim 17 (depends on 1)

The thin film transistor according to claim 1, wherein the semiconductor layers and the semiconductor layer connection lines are each formed by an organic semiconductor.

### Claim 18 (depends on 1)

The thin film transistor according to claim 1, wherein the pixel electrode is overlapped with neither the semiconductor layer nor the semiconductor layer connection line.

### Claim 19 (depends on 1)

The thin film transistor array according to claim 1, wherein the insulation substrate is a flexible substrate.

### Claim 20 (depends on 15)

The thin film transistor array according to claim 15, wherein the insulation substrate is a flexible substrate.