# US 10,374,014 B2 · Multi-state phase change memory device with vertical cross-point structure

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- Number: US 10,374,014 B2
- Document ID: US10374014B2
- Status: Granted
- Kind: B2
- Application number: 15/869,592
- Filed: 2018-01-12
- Published: 2019-04-18
- Granted: 2019-08-06
- Earliest claimed: 2017-10-16
- Assignees: SanDisk Technologies LLC
- Applicants: SanDisk Technologies LLC
- Inventors: Federico Nardi; Christopher J Petti; Gerrit Jan Hemink
- Web page: https://patentgrep.com/patent/US10374014B2

## CPC

- H10B 63/845: {the switching components being connected to a common vertical conductor}
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- H10B 63/24: {of the Ovonic threshold switching type}
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- G11C 13/0064: {Verifying circuits or methods}
- G11C 2013/005: {Read using potential difference applied between cell electrodes}
- G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse}
- G11C 2213/51: Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode
- G11C 2213/52: Structure characterized by the electrode material, shape, etc.
- G11C 2213/71: Three dimensional array
- G11C 2213/75: Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- G11C 2213/79: Array wherein the access device being a transistor
- H10D 30/6728: {Vertical TFTs}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

## Claims

### Claim 1

An apparatus, comprising:
a three-dimensional array of non-volatile memory cells formed over a substrate, comprising:
a plurality of layers of word lines, each of the layers of word lines running horizontally over the substrate, the layers separated in a vertical direction by dielectric layers;
a plurality of bit lines running vertically with respect to the substrate; and
a plurality of memory cells each connected between a corresponding one of the word lines and a corresponding one of the bit lines, each of the memory cells comprising:
a phase change memory material configured to provide a first current path between the corresponding word line and the corresponding bit line for the memory cell, the phase change memory material having a first resistivity in a first phase and a second resistivity in a second phase, the first resistivity being higher than the second resistivity; and
an intermediate resistance material adjacent to the phase change memory material and configured to provide second current path in parallel with the first current path between the memory cell's corresponding word line and bit line, the intermediate resistance material having a resistivity between the first and second resistivities; and
one or more control circuits connected to the three-dimensional array of non-volatile memory cells, the control circuits configured to program multi-state data into the memory cells and read multi-state data from the memory cells.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the one or more control circuits are configured to program a selected memory cell from an erased state to a target state by applying a current pulse across the selected memory cell high enough to raise at least a portion of the phase change memory material of the selected memory cell above melting temperature thereof across the selected memory cell, an amplitude of the current pulse dependent upon the target state.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the one or more control circuits comprise:
programming circuitry including a current mirror having a first leg connectable to the selected memory cell and a second leg connectable to a plurality of programming current levels.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the one or more control circuits are further configured to program the selected memory cell from an erased state to a target state by performing a verify operation subsequent to applying the current pulse and, based on the verify operation, applying an additional current pulse across the selected memory cell.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the one or more control circuits are configured to program a selected memory cell from an erased state to a target state by applying a current pulse across the selected memory cell high enough to raise at least a portion of the phase change memory material of the selected memory cell above melting temperature thereof across the memory cell, a duration of the current pulse dependent upon the target state.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the one or more control circuits are configured to erase a selected memory cell from an erased state to a target state by applying a current across the selected memory cell sufficient to raise a temperature of phase change memory material of the selected memory cell above a crystallization temperature, but not above a melt temperature, of the phase change memory material.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the one or more control circuits are configured to read a selected memory cell by comparing a current flowing though selected the memory cell with a reference current.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the one or more control circuits are configured to generate the current flowing through the selected memory cell in response to one of a plurality of read voltage levels.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the one or more control circuits comprise:
read circuitry including a current mirror having a first leg connectable to the selected memory cell to apply a current level thereto dependent on the one of the read voltage levels and a second leg to compare applied current level to a reference current.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein each of the memory cells further comprise:
a selector switch connected between parallel first and second current paths and the corresponding bit line.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the phase change memory material and the intermediate resistance material of each of the memory cells are confined within a pore structure in the dielectric layers.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the phase change memory material includes a chalcogenide material.

### Claim 13 (depends on 1)

The apparatus of claim 1, wherein the intermediate resistance material includes a metal-nitride.

### Claim 14

A non-volatile memory device, comprising:
a memory array having a three-dimensional, vertical cross-point architecture of multi-state memory cells disposed horizontally between word lines and bit lines, each of the memory cells comprising a phase change memory material confined within a pocket lined with a surfactant within a dielectric material; and
one or more control circuits, including read circuitry configured to read a read selected multi-state memory cell by comparing a current flowing though the read selected memory cell with a reference current and write circuitry configured to program a write selected memory cell from an erased state to a one of a plurality of target states by applying a current pulse across the write selected memory cell high enough to raise at least a portion of the phase change memory material of the write selected memory cell above a melting temperature thereof.

### Claim 15 (depends on 14)

The non-volatile memory device of claim 14, the read circuitry including a current mirror having a first leg connectable to the read selected memory cell to apply a current level thereto dependent on the one of a plurality of read voltage levels and a second leg to compare applied current level to a reference current.

### Claim 16 (depends on 14)

The non-volatile memory device of claim 14, wherein an amplitude of the current pulse dependent upon the target state.

### Claim 17 (depends on 16)

The non-volatile memory device of claim 16, the write circuitry including a current mirror having a first leg connectable to the write selected memory cell and a second leg connectable to a plurality of programming current levels.

### Claim 18 (depends on 14)

The non-volatile memory device of claim 14, the control circuits further comprising erase circuitry configured to erase an erase selected memory cell from any of the plurality of target states to the erased state by applying a current across the erase selected memory cell sufficient to raise a temperature of phase change memory material of the erase selected memory cell above a crystallization temperature, but not above the melting temperature, of the phase change memory material.

### Claim 19 (depends on 14)

The non-volatile memory of claim 14, wherein the phase change memory material includes a chalcogenide material.

### Claim 20

A non-volatile memory device, comprising:
a memory array, comprising:
a plurality of word lines running in a horizontal direction;
a plurality of bit lines running in a vertical direction; and
a plurality of multi-state memory cells each connected between a corresponding word line and a corresponding bit line, each of the memory cells comprising:
a phase change memory material having a first resistivity in a first phase and a second resistivity in a second phase, the first resistivity being higher than the second resistivity; and
means for providing an additional current path adjacent to the phase change memory material having a resistivity higher than the second resistivity and lower than the first resistivity; and
means for reading a data state stored in each of the multi-state memory cells; and
means for writing one of a plurality of data states to each of multi-state memory cells by applying a current pulse having an amplitude dependent upon the data state to which the multi-state memory cell is to be programmed.