# US 10,374,013 B2 · Methods and apparatus for three-dimensional nonvolatile memory

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,374,013 B2
- Document ID: US10374013B2
- Status: Granted
- Kind: B2
- Application number: 15/473,671
- Filed: 2017-03-30
- Published: 2018-10-04
- Granted: 2019-08-06
- Earliest claimed: 2017-03-30
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Abhijit Bandyopadhyay; Christopher J. Petti; Natalie Nguyen; Brian Le
- Web page: https://patentgrep.com/patent/US10374013B2

## CPC

- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/884: {based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors (compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883)}
- H10W 20/0698: {Local interconnections}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method is provided that includes forming a bit line above a substrate; forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. The isolation element includes a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.

## Claims

### Claim 1

A method comprising:
forming a bit line above a substrate;
forming a word line above the substrate;
etching the word line to form a void adjacent an end of the word line;
forming a non-volatile memory material in the void; and
forming a non-volatile memory cell between the bit line and the word line, the non-volatile memory cell comprising the non-volatile memory material coupled in series with an isolation element,
wherein:
the isolation element comprises a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.

### Claim 2 (depends on 1)

The method of claim 1, wherein the isolation element further comprises a first capping layer disposed between the semiconductor layer and the barrier layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the isolation element further comprises a second capping layer disposed between the semiconductor layer and the second electrode.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first electrode comprises one or more of copper, silver, and nickel.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second electrode comprises one or more of titanium nitride, a conductive carbon, platinum, ruthenium, palladium, iridium, titanium aluminum nitride, and tungsten.

### Claim 6 (depends on 1)

The method of claim 1, wherein the semiconductor layer comprises one or more of silicon, germanium, silicon-germanium, hafnium oxide, silicon oxide, titanium oxide, tungsten oxide and zinc oxide.

### Claim 7 (depends on 1)

The method of claim 1, wherein the barrier layer comprises one or more of titanium, tantalum, titanium nitride, tantalum nitride, tungsten nitride, and tantalum carbide.

### Claim 8 (depends on 1)

The method of claim 1, wherein the bit line comprises the first electrode or the second electrode.

### Claim 9 (depends on 1)

The method of claim 1, wherein the non-volatile memory material comprises a reversible resistance-switching memory element.

### Claim 10 (depends on 1)

The method of claim 1, wherein the non-volatile memory material comprises one or more of a phase change material, a ferroelectric material, a metal oxide, and a barrier modulated switching structure.

### Claim 11

A method comprising:
forming a bit line disposed in a first direction above a substrate;
forming a word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction;
etching the word line to form a void at an end of the word line; and
forming a non-volatile memory cell at an intersection of the bit line and the word line by:
forming a non-volatile memory material in the void; and
forming an isolation element adjacent the non-volatile memory material, the isolation element comprising a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.

### Claim 12 (depends on 11)

The method of claim 11, wherein the isolation element further comprises a first capping layer disposed between the semiconductor layer and the barrier layer.

### Claim 13 (depends on 11)

The method of claim 11, wherein the isolation element further comprises a second capping layer disposed between the semiconductor layer and the second electrode.

### Claim 14 (depends on 11)

The method of claim 11, wherein the first electrode comprises one or more of copper, silver, and nickel.

### Claim 15 (depends on 1)

The method of claim 1, wherein the semiconductor layer comprises one or more of silicon, germanium, silicon-germanium, hafnium oxide, silicon oxide, titanium oxide, tungsten oxide and zinc oxide.

### Claim 16 (depends on 11)

The method of claim 11, wherein the barrier layer comprises one or more of titanium, tantalum, titanium nitride, tantalum nitride, tungsten nitride, and tantalum carbide.

### Claim 17 (depends on 1)

The method of claim 1, wherein the non-volatile memory material comprises a reversible resistance-switching memory element.

### Claim 18 (depends on 1)

The method of claim 1, wherein the non-volatile memory material comprises one or more of a phase change material, a ferroelectric material, a metal oxide, and a barrier modulated switching structure.