# US 10,374,012 B2 · Electronic device and method of fabricating the same

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- Number: US 10,374,012 B2
- Document ID: US10374012B2
- Status: Granted
- Kind: B2
- Application number: 16/030,619
- Filed: 2018-07-09
- Published: 2019-05-23
- Granted: 2019-08-06
- Earliest claimed: 2017-11-17
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Dong Hoon Kim
- Web page: https://patentgrep.com/patent/US10374012B2

## CPC

- G11C 13/0026: {Bit-line or column circuits}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 8/14: Word line organisation; Word line lay-out
- G11C 11/1655: {Bit-line or column circuits}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 2213/71: Three dimensional array
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided herein may be an electronic device including a semiconductor memory. The semiconductor memory may include: first column lines and sub-column lines extending in a first direction; first row lines extending in a second direction; first tiles including first memory cells connected between the first column lines and the first row lines; first contact plugs coupled to the sub-column lines and disposed between the first tiles in the first direction; second contact plugs coupled to the first row lines and disposed between the first tiles in the second direction; and a first connection structure partially coupling the first column lines to the sub-column lines such that the longer a current path on a first row line from a selected first memory cell to the corresponding second contact plug, the shorter a current path from the selected first memory cell to the corresponding first contact plug.

## Claims

### Claim 1

An electronic device comprising a semiconductor memory,
wherein the semiconductor memory comprises:
first column lines extending in a first direction;
sub-column lines extending in the first direction;
first row lines extending in a second direction intersecting with the first direction;
first tiles including first memory cells connected between the first column lines and the first row lines;
first contact plugs disposed between the first tiles that are adjacent to each other in the first direction, the first contact plugs being coupled to the sub-column lines;
second contact plugs disposed between the first tiles that are adjacent to each other in the second direction, the second contact plugs being coupled to the first row lines; and
a first connection structure coupled between the first column lines and the sub-column lines at predetermined locations such that, as a length of a current path on a first row line from a selected first memory cell to a corresponding second contact plug increases, a length of a current path from the selected first memory cell to a corresponding first contact plug decreases.

### Claim 2 (depends on 1)

The electronic device according to claim 1, further comprising:
a column circuit coupled to the first column lines through the first contact plugs and the sub-column lines; and
a row circuit coupled to the first row lines through the second contact plugs.

### Claim 3 (depends on 1)

The electronic device according to claim 1, wherein the first row lines, the first column lines, and the sub-column lines are successively stacked.

### Claim 4 (depends on 1)

The electronic device according to claim 1, wherein each of the first column lines is a bit line, each of the sub-column lines is a sub-bit line, and each of the first row lines is a word line.

### Claim 5 (depends on 1)

The electronic device according to claim 1, further comprising:
second column lines extending in the first direction;
second row lines extending in the second direction;
second tiles including second memory cells connected between the second column lines and the second row lines, the second tiles being disposed over the first tiles;
third contact plugs disposed between the second tiles that are adjacent to each other in the second direction, the third contact plugs being coupled to the second row lines; and
a second connection structure that couples the second column lines to the sub-column lines at predetermined locations such that, as a length of a current path on a second row line from a selected second memory cell to a corresponding third contact plug increases, a length of a current path from the selected second memory cell to a corresponding first contact plug decreases.

### Claim 6 (depends on 5)

The electronic device according to claim 5, further comprising:
a column circuit coupled to the second column lines through the first contact plugs and the sub-column lines; and
a row circuit coupled to the second row lines through the third contact plugs.

### Claim 7 (depends on 5)

The electronic device according to claim 5, wherein the first row lines, the first column lines, the sub-column lines, the second column lines, and the second row lines are successively stacked.

### Claim 8 (depends on 5)

The electronic device according to claim 5, wherein each of the first column lines is a bit line, each of the sub-column lines is a sub-bit line, each of the first row lines is a word line, each of the second column lines is a bit line, and each of the second row lines is a word line.

### Claim 9 (depends on 5)

The electronic device according to claim 5, wherein the second contact plugs and the third contact plugs are alternately arranged in the second direction without overlapping with each other in a stacking direction.

### Claim 10 (depends on 1)

The electronic device according to claim 1, further comprising:
second row lines extending in the second direction;
sub-row lines extending in the second direction;
second tiles including second memory cells connected between the sub-column lines and the second row lines, the second tiles being disposed under the first tiles;
third contact plugs disposed between the second tiles that are adjacent to each other in the second direction, the third contact plugs being coupled to the sub-row lines; and
a second connection structure coupled between the sub-row lines and the second row lines such that, as a length of a current path on a sub-column line from a selected second memory cell to a corresponding first contact plug increases, a length of a current path from the selected second memory cell to a corresponding third contact plug decreases.

### Claim 11 (depends on 10)

The electronic device according to claim 10, further comprising:
a column circuit coupled with the sub-column lines through the first contact plugs; and
a row circuit coupled with the second row lines through the third contact plugs and the sub-row lines.

### Claim 12 (depends on 10)

The electronic device according to claim 10, wherein the sub-row lines, the second row lines, the sub-column lines, the first column lines, and the first row lines are successively stacked.

### Claim 13 (depends on 10)

The electronic device according to claim 10, wherein each of the first column lines is a bit line, each of the sub-column lines is a sub-bit line, each of the first row lines is a word line, each of the sub-row lines is a sub-word line, and each of the second row lines is a word line.

### Claim 14 (depends on 10)

The electronic device according to claim 10, wherein the second contact plugs and the third contact plugs are alternately arranged in the second direction without overlapping with each other in a stacking direction.

### Claim 15 (depends on 1)

The electronic device according to claim 1, further comprising:
second row lines extending in the second direction;
second tiles including second memory cells connected between the sub-column lines and the second row lines, the second tiles being disposed over the first tiles; and
third contact plugs disposed between the second tiles that are adjacent to each other in the second direction, the third contact plugs being coupled to the second row lines.

### Claim 16

An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises:
a first deck including first memory cells;
a second deck disposed over the first deck, and including second memory cells;
a first column line electrically coupled to the first memory cells;
a second column line electrically coupled to the second memory cells;
a sub-column line disposed between the first deck and the second deck and coupled to a column circuit that drives the first column line and the second column line;
a first connection structure coupled between the first column line and the sub-column line; and
a second connection structure coupled between the second column line and the sub-column line.

### Claim 17 (depends on 16)

The electronic device according to claim 16, further comprising a first row line electrically coupled to the first memory cells and driven by a row circuit.

### Claim 18 (depends on 17)

The electronic device according to claim 17, wherein the first connection structure is configured such that, as a path on the first row line from the row circuit to a selected first memory cell increases, a distance from the column circuit to a position at which the first column line is coupled to the sub-column line decreases, and, as the path on the first row line from the row circuit to the selected first memory cell decreases, the distance from the column circuit to the position at which the first column line is coupled to the sub-column line increases.

### Claim 19 (depends on 16)

The electronic device according to claim 16, further comprising a second row line electrically coupled to the second memory cells and configured to be driven by a row circuit.

### Claim 20 (depends on 19)

The electronic device according to claim 19, wherein the second connection structure is configured such that, as a path on the second row line from the row circuit to a selected second memory cell increases, a distance from the column circuit to a position at which the second column line is coupled to the sub-column line decreases, and, as the path on the second row line from the row circuit to the selected second memory cell decreases, the distance from the column circuit to the position at which the second column line is coupled to the sub-column line increases.