# US 10,374,007 B2 · Memory including a selector switch on a variable resistance memory cell

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,374,007 B2
- Document ID: US10374007B2
- Status: Granted
- Kind: B2
- Application number: 15/918,770
- Filed: 2018-03-12
- Published: 2018-09-27
- Granted: 2019-08-06
- Earliest claimed: 2009-11-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Andrea Redaelli; Agostino Pirovano
- Web page: https://patentgrep.com/patent/US10374007B2

## CPC

- G11C 13/00: Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0014: {comprising cells based on organic memory material}
- G11C 13/0016: {comprising polymers}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10K 19/00: Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8418: {adapted for focusing electric field or current, e.g. tip-shaped}
- H10N 70/881: {Switching materials}
- H10N 70/882: {Compounds of sulfur, selenium or tellurium, e.g. chalcogenides}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- G11C 2213/72: Array wherein the access device being a diode
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.

## Claims

### Claim 1

A method comprising:
forming a sealing layer on a portion of a selector switch and a portion of a memory cell;
forming a plurality of dielectric layers in contact with a portion of the memory cell;
forming a conductive plug in contact with and disposed on a portion of a surface of the sealing layer; and
forming a diffusion barrier in contact with a pair of sidewalls of the conductive plug.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming the selector switch in contact with and disposed on the portion of the memory cell.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the selector switch further comprises:
forming a first metal layer; and
forming a first non-silicon-based semiconductor layer in contact with an upper surface of the first metal layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein forming the selector switch further comprises:
forming a second metal layer; and
forming a second non-silicon-based semiconductor layer disposed between the first non-silicon-based semiconductor layer and the second metal layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the second non-silicon-based semiconductor layer is in contact with an upper surface of the first non-silicon-based semiconductor layer and a lower surface of the second metal layer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming an upper electrode layer;
forming a variable resistance memory layer in contact with a lower surface of the upper electrode layer; and
forming a lower electrode layer in contact with a lower surface of the variable resistance memory layer,
wherein the variable resistance memory layer is disposed between the upper electrode layer and the lower electrode layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the sealing layer further comprises:
forming the sealing layer on a surface and at least one sidewall of the selector switch and at least one sidewall of the memory cell.

### Claim 8 (depends on 1)

The method of claim 1, wherein a portion of each dielectric layer of the plurality of dielectric layers is in contact with a portion of the sealing layer.

### Claim 9

A memory array comprising:
a plurality of memory cells, each memory cell of the plurality coupled with a corresponding bit line and a corresponding word line;
a plurality of selector switches, each selector switch of the plurality in contact with a corresponding memory cell of the plurality;
a sealing layer in contact with an upper surface and a pair of sidewalls of each of the selector switches and a pair of sidewalls of each of the memory cells;
a plurality of conductive plugs, each conductive plug of the plurality in contact with a corresponding memory cell of the plurality and disposed on a portion of the sealing layer; and
a plurality of diffusion barriers, each diffusion barrier in contact with a corresponding conductive plug of the plurality.

### Claim 10 (depends on 9)

The memory array of claim 9, wherein each selector switch of the plurality comprises a first metal layer and a first non-silicon-based semiconductor layer in contact with an upper surface of the first metal layer.

### Claim 11 (depends on 10)

The memory array of claim 10, wherein each selector switch of the plurality comprises a second metal layer and a second non-silicon-based semiconductor layer disposed between the first non-silicon-based semiconductor layer and the second metal layer.

### Claim 12 (depends on 9)

The memory array of claim 9, wherein each conductive plug of the plurality is configured to pass electrical current between a corresponding selector switch and a corresponding word line.

### Claim 13 (depends on 9)

The memory array of claim 9, further comprising:
a second plurality of memory cells, each memory cell of the second plurality coupled with a corresponding second bit line and a corresponding second word line;
a second plurality of selector switches, each selector switch of the second plurality in contact with a corresponding memory cell of the second plurality;
a second sealing layer in contact with an upper surface and a pair of sidewalls of each of the selector switches of the second plurality and a pair of sidewalls of each of the memory cells of the second plurality,
wherein each memory cell of the plurality is at a first level of the memory array and each memory cell of the second plurality is at a second level of the memory array.

### Claim 14 (depends on 9)

The memory array of claim 9, further comprising:
a plurality of second conductive plugs, each second conductive plug in contact with a lower surface of a corresponding memory cell of the second plurality, wherein the second conductive plugs are configured to pass electrical current between the corresponding memory cell of the second plurality and a corresponding second bit line.

### Claim 15

A method for forming a memory device, comprising:
forming a sealing layer on a surface and a pair of sidewalls of a selector switch and a pair of sidewalls of a memory cell;
forming a conductive plug in contact with and disposed on a portion of a surface of the sealing layer; and
forming a diffusion barrier in contact with a pair of sidewalls of the conductive plug.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming the selector switch on a portion of the memory cell, wherein the sealing layer is formed after the memory cell and the selector switch.

### Claim 17 (depends on 16)

The method of claim 16, wherein the selector switch is in contact with and disposed on the portion of the memory cell.

### Claim 18 (depends on 15)

The method of claim 15, wherein the conductive plug is in contact with and disposed on an upper surface of the sealing layer.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
forming a second conductive plug in contact with a lower surface of the memory cell; and
forming a second diffusion barrier in contact with a pair of sidewalls of the second conductive plug.

### Claim 20 (depends on 15)

The method of claim 15, wherein the conductive plug comprises a first metal material and the second conductive plug comprises a second metal material different from the first metal material.