# US 10,373,989 B2 · Thin-film transistor array substrate and manufacturing method thereof

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- Number: US 10,373,989 B2
- Document ID: US10373989B2
- Status: Granted
- Kind: B2
- Application number: 15/834,077
- Filed: 2017-12-07
- Published: 2018-04-05
- Granted: 2019-08-06
- Earliest claimed: 2015-04-27
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Xiaowen Lv; Chihyu Su
- Web page: https://patentgrep.com/patent/US10373989B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/01: Manufacture or treatment
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10P 50/282: {of inorganic materials}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A thin-film transistor (TFT) array substrate includes a TFT arrangement and a storage capacitor. A gate insulation layer has a portion interposed between two electrode plates of the storage capacitor and thinner than a remaining portion of the gate insulation layer and thus, the thickness of insulation between the electrode plates of the storage capacitor is reduced so that the area of the opposite surfaces of the capacitor can be made smaller and an increased aperture ratio can be achieved.

## Claims

### Claim 1

A thin-film transistor array substrate, comprising a base plate having a surface and a thin-film transistor arrangement and a storage capacitor formed on the surface of the base plate;
wherein the thin-film transistor arrangement comprises at least one gate terminal arranged on the surface of the base plate and at least one oxide semiconductor layer corresponding to and located above the at least one gate terminal;
wherein the storage capacitor comprises a first electrode plate arranged on the surface of the base plate and spaced from the at least one gate terminal of the thin-film transistor arrangement to define an intermediate area of the surface of the base plate therebetween, a second electrode plate located above the first electrode plate, a gate insulation layer located between the first electrode plate and the second electrode plate and arranged on the first electrode plate, an etch stop layer located between the first electrode plate and the second electrode plate and arranged on the gate insulation layer;
wherein the gate insulation layer has a transistor-related portion that is located on the at least one gate terminal and interposed between the at least one gate terminal and the at least one oxide semiconductor layer, a capacitor-related portion that corresponds to and is located on the first electrode plate, and an intermediate connection portion integrally connected with the transistor-related portion and the capacitor-related portion and partly arranged on the intermediate area of the surface of the base plate to extend between the thin-film transistor arrangement and the storage capacitor, wherein the capacitor-related portion of the gate insulation layer has a thickness that is smaller than a thickness of the intermediate connection portion of the gate insulation layer that is arranged on the intermediate area of the surface of the base plate and extends between the thin-film transistor arrangement and the storage capacitor, the capacitor-related portion of the gate insulation layer being located atop the first electrode plate, such that a top of the capacitor-related portion of the gate insulation layer is spaced from the surface of the base plate by a first distance that is larger than a second distance by which a top of the immediate connection portion of the gate insulation layer is spaced from the surface of the base plate; and
wherein the etch stop layer is partly arranged atop the at least one oxide semiconductor layer of the thin-film transistor arrangement and extends through the intermediate area of the surface of the base plate to the first electrode plate of the storage capacitor, such that the etch stop has a first portion that is located on the capacitor-related portion of the gate insulation layer and has a top surface that is substantially consistent with a top surface of a second portion of the etch stop layer that extends from the thin-film transistor arrangement to the storage capacitor and is located on the intermediate connection portion of the gate insulation layer on the intermediate area of the surface of the base plate, the first portion and the second portion of the etch stop layer having, respectively, a first material thickness and a second material thickness that are different from each other, such that a difference between the first material thickness and the second material thickness equals to a difference between the first distance and the second distance by which the capacitor-related portion and the immediate connection portion of the gate insulation layer are spaced from the surface of the base plate in order to provide a substantially continuous flat surface between the first portion and the second portion of the etch stop layer that correspond to the capacitor-related portion and the immediate connection portion of the gate insulation layer, wherein the second electrode plate is formed on the etch top layer; and
wherein a combination of the capacitor-related portion of the gate insulation layer and the first portion of the etch stop layer that are interposed between the first and second electrode plates has an overall thickness that is smaller than an overall thickness of a combination of the immediate connection portion of the gate insulation layer and the second portion of the etch stop layer that are located in the intermediate area of the surface of the base plate.

### Claim 2 (depends on 1)

The thin-film transistor array substrate as claimed in claim 1,
wherein the at least one gate terminal comprises a first gate terminal and a second gate terminal that are arranged on the surface of the base plate such that the first electrode plate is located at one side of the second gate terminal that is distant from the first gate terminal and is spaced from the second gate terminal to define the free area of the surface of the base plate therebetween, wherein the gate insulation layer is arranged on the first gate terminal, the second gate terminal, the first electrode plate, and the base plate;
wherein the at least one oxide semiconductor layer comprises a first oxide semiconductor layer and a second oxide semiconductor layer that are arranged on the gate insulation layer and respectively located above the first gate terminal and the second gate terminal, wherein the etch stop layer is arranged on the first oxide semiconductor layer, the second oxide semiconductor layer, and the gate insulation layer; and
a first source terminal that are arranged on the etch stop and located above the first gate terminal and are respectively in contact with two opposite ends of the first oxide semiconductor layer, and a second drain terminal that are arranged on the etch stop layer and located above the second gate terminal and are respectively in contact with two opposite ends of the second oxide semiconductor layer;
wherein the gate insulation layer comprises a first via formed therein to be corresponding to and located above a side portion of the second gate terminal that is adjacent to the first gate terminal and the first source terminal is set in contact engagement with the second gate terminal through the first via; and
wherein the first gate terminal, the gate insulation layer, the first oxide semiconductor layer, the etch stop layer, the first source terminal, the first drain terminal collectively form a first thin-film transistor part of the thin-film transistor arrangement; and the second gate terminal, the gate insulation layer, the second oxide semiconductor layer, the etch stop layer, the second source terminal, and the second drain terminal collectively form a second thin-film transistor part of the thin-film transistor arrangement.

### Claim 3 (depends on 2)

The thin-film transistor array substrate as claimed in claim 2 further comprising:
a passivation layer that is arranged on the first source terminal, the first drain terminal, the second source terminal, the second drain terminal, and the second electrode plate and coves the etch stop layer;
a planarization layer that is arranged on the passivation layer;
a pixel electrode layer that is arranged on the planarization layer;
a pixel definition layer that is arranged on the planarization layer and the pixel electrode layer; and
a photoresist spacer that is arranged on the pixel definition layer;
wherein the passivation layer and the planarization layer comprise a second via formed therein to be corresponding to and located above the second source terminal and the pixel definition layer comprises a third via formed therein to being corresponding to and located above the pixel electrode layer, wherein the pixel electrode layer is set in contact engagement with the second source terminal through the second via and the third via exposes a portion of the pixel electrode layer.

### Claim 4 (depends on 1)

The thin-film transistor array substrate as claimed in claim 1, wherein the gate insulation layer comprises a material of one of aluminum oxide, silicon nitride, and silicon oxide, or a combination thereof.