# US 10,373,984 B2 · Display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,984 B2 - Document ID: US10373984B2 - Status: Granted - Kind: B2 - Application number: 15/895,139 - Filed: 2018-02-13 - Published: 2018-10-04 - Granted: 2019-08-06 - Earliest claimed: 2017-03-29 - Assignees: Japan Display Inc. - Applicants: Japan Display Inc. - Inventors: Yohei Yamaguchi - Web page: https://patentgrep.com/patent/US10373984B2 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/133345: {Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence)} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes} - H10D 30/6729: {characterised by the electrodes} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics} - H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs} - G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]} - G02F 1/136295: {Materials; Compositions; Manufacture processes} - G02F 1/13685: {Top gates} - G02F 2202/10: semiconductor - G02F 2202/104: poly-Si - H10D 30/6731: {Top-gate only TFTs} - H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs} - H10D 30/6745: {Polycrystalline or microcrystalline silicon} - H10K 59/1213: {the pixel elements being TFTs} - H10K 2102/00: Constructional details relating to the organic devices covered by this subclass - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract The purpose of the present invention is to improve reliability of the TFT of the oxide semiconductor. The feature of the invention is: A display device comprising: a substrate including a display area where plural pixels are formed, the pixel includes a first TFT of a first oxide semiconductor, a first gate insulating film is formed under the first oxide semiconductor, a first gate electrode is formed under the first gate insulating film, an interlayer insulating film is formed on the first oxide semiconductor; a drain wiring, which connects with the first oxide semiconductor, and a source wiring, which connects with the first oxide semiconductor, are formed on the interlayer insulating film; the drain wiring or the source wiring is a laminated structure of a second oxide semiconductor and a first metal, the second oxide semiconductor is under the first metal. ## Claims ### Claim 1 A display device comprising: a substrate including a display area where plural pixels are formed, the plural pixels include a first TFT of a first oxide semiconductor, a first gate insulating film is formed under the first oxide semiconductor, a first gate electrode is formed under the first gate insulating film, an interlayer insulating film is formed on the first oxide semiconductor, a first through hole and a second through hole are formed across the interlayer insulating film in a direction facing the substrate and the plural pixels, a drain wiring, which connects with the first oxide semiconductor through the first through hole, and a source wiring, which connects with the first oxide semiconductor through the second through hole, are formed on the interlayer insulating film, the drain wiring or the source wiring is a laminated structure of a second oxide semiconductor and a first metal, the second oxide semiconductor is under the first metal, and the laminated structure of the drain wiring contacts a side wall of the first through hole, the laminated structure of the source wiring contacts a side wall of the second through hole. ### Claim 2 (depends on 1) The display device according to claim 1, wherein the interlayer insulating film is a laminated structure of a first silicon oxide film and a first aluminum oxide film, the first silicon oxide film is under the first aluminum oxide film. ### Claim 3 (depends on 1) The display device according to claim 1, wherein the interlayer insulating film is a laminated structure of a first silicon oxide film and a first silicon nitride film, the first silicon oxide film is under the first silicon nitride film. ### Claim 4 (depends on 1) The display device according to claim 1, wherein the first gate insulating film is a laminated structure of a second aluminum oxide film and a second silicon oxide film, the second silicon oxide film is over the second aluminum oxide film. ### Claim 5 (depends on 1) The display device according to claim 1, wherein the first gate electrode is a laminated structure of a second metal layer and a third oxide semiconductor, the second metal layer is under the third oxide semiconductor. ### Claim 6 (depends on 1) The display device according to claim 1, wherein the substrate includes a second TFT of a poly-silicon semiconductor, a distance between the poly-silicon semiconductor d the substrate is less than a distance between the first oxide semiconductor and the substrate. ### Claim 7 A display device comprising: a substrate including a display area where plural pixels are formed, the plural pixels include a first TFT of a first oxide semiconductor, a first gate insulating film is formed on the first oxide semiconductor, a first gate electrode is formed on the first gate insulating film, an interlayer insulating film is formed on the first gate electrode, a first through hole and a second through hole are formed across the interlayer insulating film in a direction facing the substrate and the plural pixels, a drain wiring, which connects with the first oxide semiconductor through the first through hole, and a source wiring, which connects with the first oxide semiconductor through the second through hole, are formed on the interlayer insulating film, the drain wiring or the source wiring is a laminated structure of a second oxide semiconductor and a first metal, the second oxide semiconductor is under the first metal, and the laminated structure of the drain wiring contacts a side wall of the first through hole, the laminated structure of the source wiring contacts a side wall of the second through hole. ### Claim 8 (depends on 7) The display device according to claim 7, a protective layer is formed between the first oxide semiconductor layer and the drain wiring, and between the first oxide semiconductor layer and the source wiring. ### Claim 9 (depends on 7) The display device according to claim 7, wherein the interlayer insulating film is a laminated structure of a first silicon oxide film and a first aluminum oxide film, the first silicon oxide film is under the first aluminum oxide film. ### Claim 10 (depends on 7) The display device according to claim 7, wherein the interlayer insulating film is a laminated structure of a first silicon oxide film and a first silicon nitride film, the first silicon oxide film is under the first silicon nitride film. ### Claim 11 (depends on 7) The display device according to claim 7, wherein the first gate insulating film is a laminated structure of a second aluminum oxide film and a second silicon oxide film, the second silicon oxide film is under the second aluminum oxide film. ### Claim 12 (depends on 7) The display device according to claim 7, wherein the first gate electrode is a laminated structure of a second metal layer and a third oxide semiconductor, the second metal layer is on the third oxide semiconductor. ### Claim 13 (depends on 7) The display device according to claim 7, wherein the substrate includes a second TFT of a poly-silicon semiconductor, a distance between the poly-silicon semiconductor d the substrate is less than a distance between the first oxide semiconductor and the substrate. ### Claim 14 (depends on 8) The display device according to claim 8, wherein the substrate includes a second TFT of a poly-silicon semiconductor, a distance between the poly-silicon semiconductor and the substrate is less than a distance between the first oxide semiconductor and the substrate. ### Claim 15 (depends on 7) The display device according to claim 7, a second gate insulating film including a third silicon oxide film, a second gate electrode is formed under the second gate insulating film, the first oxide semiconductor film is formed on the third silicon oxide film. ### Claim 16 (depends on 15) The display device according to claim 15, the second gate insulating film is a laminated turn of the third silicon oxide film and a third aluminum oxide film, the second gate electrode contacts with the aluminum oxide film. ### Claim 17 (depends on 15) The display device according to claim 15, the second gate electrode is formed by a laminated film of a second metal layer and a third oxide semiconductor film, the third oxide semiconductor film is on the second metal layer. ### Claim 18 (depends on 8) The display device according to claim 8, a second gate insulating film including a third silicon oxide film is formed under the first oxide semiconductor, a second gate electrode is formed under the second gate insulating film, the first oxide semiconductor is formed on the third silicon oxide film. ### Claim 19 (depends on 15) The display device according to claim 15, wherein the substrate includes a second TFT of a poly-silicon semiconductor, a distance between the poly-silicon semiconductor and the substrate is less than a distance between the second gate electrode and the substrate. ### Claim 20 (depends on 18) The display device according to claim 18, wherein the substrate includes a second TFT of a poly-silicon semiconductor, a distance between the poly-silicon semiconductor and the substrate is less than a distance between the second gate electrode and the substrate.