# US 10,373,977 B2 · Transistor fin formation via cladding on sacrificial core

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- Number: US 10,373,977 B2
- Document ID: US10373977B2
- Status: Granted
- Kind: B2
- Application number: 15/576,393
- Filed: 2015-06-26
- Published: 2018-06-07
- Granted: 2019-08-06
- Earliest claimed: 2015-06-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Glenn A. Glass; Anand S. Murthy; Daniel B. Aubertine; Tahir Ghani; Jack T. Kavalieros; Benjamin Chu-Kung; Chandra S. Mohapatra; Karthik Jambunathan; Gilbert Dewey; Willy Rachmady
- Web page: https://patentgrep.com/patent/US10373977B2

## CPC

- H10D 86/215: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 86/011: {comprising FinFETs}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.

## Claims

### Claim 1

An integrated circuit device, comprising:
a substrate having one or both of (i) a plurality of covered fins extending from the substrate and/or (ii) a plurality of covered recesses extending into the substrate, wherein each covered fin and/or recess is covered by an insulation layer; and
a fin-pair above each covered fin and/or recess, each fin-pair comprising a semiconductor material, wherein the insulation layer is between the substrate and the fin-pair, such that a thickness of the insulation layer separates each fin-pair from its underlying covered fin or recess.

### Claim 2 (depends on 1)

The device of claim 1 wherein the covered fins comprise a material different than the substrate, and wherein the covered fins comprise at least one of silicon fins, silicon germanium fins, germanium fins, and III-V material fins.

### Claim 3 (depends on 1)

The device of claim 1 wherein the covered fins comprise native fins that are part of the substrate.

### Claim 4 (depends on 1)

The device of claim 1 wherein each of the fin-pairs includes two fins separated by a distance that is substantially the same as the width of the underlying covered fin or recess.

### Claim 5 (depends on 1)

The device of claim 1 wherein at least some of the covered fins are silicon fins and the semiconductor material of the fin-pairs above those silicon fins comprises silicon and germanium.

### Claim 6 (depends on 1)

The device of claim 1 wherein at least some of the covered fins comprise silicon and germanium and the semiconductor material of the fin-pairs above those covered fins is germanium.

### Claim 7 (depends on 1)

The device of claim 1 wherein at least some of the covered fins comprise gallium and arsenic and the semiconductor material of the fin-pairs above those covered fins comprises indium, gallium, and arsenic.

### Claim 8 (depends on 1)

The device of claim 1 wherein at least some of the covered fins comprise indium and phosphorous and the semiconductor material of the fin-pairs above those covered fins comprises indium, gallium, and arsenic.

### Claim 9 (depends on 1)

The device of claim 1 wherein at least some of the covered fins comprise gallium and antimony and the semiconductor material of the fin-pairs above those covered fins comprises indium and antimony.

### Claim 10 (depends on 1)

The device of claim 1 wherein the substrate is a bulk silicon substrate, and the covered fins comprise native silicon fins, and the semiconductor material of the fin-pairs above those native silicon fins comprises silicon and germanium.

### Claim 11 (depends on 1)

The device of claim 1 wherein the substrate is a bulk silicon substrate, and the covered fins comprise silicon and germanium fins, and the semiconductor material of the fin-pairs above those covered fins is germanium.

### Claim 12 (depends on 1)

The device of claim 1 wherein the substrate is a bulk silicon substrate, and the covered fins comprise III-V material fins, and the semiconductor material of the fin-pairs above those covered fins is III-V material different from the covered fin III-V material.

### Claim 13

An integrated circuit device, comprising:
a substrate having a plurality of fins covered by a shallow trench isolation (STI) region;
a fin-pair above each covered fin, each fin-pair comprising a semiconductor material, wherein a thickness of an insulator material of the STI region is between the substrate and the fin-pair and separates each fin-pair from its underlying covered fin;
a transistor gate structure on each fin of the fin-pair; and
a transistor source and a transistor drain.

### Claim 14 (depends on 13)

The device of claim 13 wherein the covered fins comprise replacement fins comprising a material different than the substrate.

### Claim 15 (depends on 14)

The device of claim 14 wherein the replacement fins comprise at least one of silicon fins, silicon germanium fins, germanium fins, and III-V material fins.

### Claim 16 (depends on 13)

The device of claim 13 wherein the covered fins comprise native fins that are part of the substrate.

### Claim 17 (depends on 13)

The device of claim 13 wherein the substrate is a bulk substrate, and each of the fin-pairs includes two fins separated by a distance that is substantially the same as the width of the underlying covered fin.

### Claim 18

An integrated circuit device, comprising:
a substrate having one or both of (i) a covered fin extending from the substrate and/or (ii) a covered recess extending into the substrate, wherein the covered fin and/or recess is covered by an insulation layer; and
a fin-pair above the covered fin and/or fin-pair above the covered recess, each fin-pair comprising a semiconductor material, wherein the insulation layer is between the substrate and each fin-pair, such that a thickness of the insulation layer separates each fin-pair from its underlying covered fin or recess.

### Claim 19 (depends on 18)

The device of claim 18 wherein the substrate is a bulk silicon substrate, and the covered fin is a silicon fin, and the semiconductor material of the fin-pair above the silicon fin comprises one or both of silicon and germanium.

### Claim 20 (depends on 18)

The device of claim 18 wherein the substrate is a bulk silicon substrate, and the covered fin is a silicon fin, and the semiconductor material of the fin-pair above the silicon fin comprises one or more of gallium, indium, antimony, and arsenic.