# US 10,373,975 B2 · Memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,975 B2 - Document ID: US10373975B2 - Status: Granted - Kind: B2 - Application number: 16/162,720 - Filed: 2018-10-17 - Published: 2019-02-14 - Granted: 2019-08-06 - Earliest claimed: 2015-12-24 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Seok Cheon Baek; Young Woo Kim; Dong Sik Lee; Min Yong Lee; Woong Seop Lee - Web page: https://patentgrep.com/patent/US10373975B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/30: characterised by the memory core region - H10B 41/40: characterised by the peripheral circuit region - H10B 43/10: characterised by the top-view layout - H10B 43/30: characterised by the memory core region - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10W 20/42: Vias, e.g. via plugs - H10W 20/43: Layouts of interconnections - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A memory device may include multiple channel regions extending in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate to be adjacent at least a portion of the plurality of channel regions, an interlayer insulating layer disposed on the plurality of gate electrode layers, a plurality of cell contact plugs passing through the interlayer insulating layer. Each of the plurality of cell contacts is connected to each of the plurality of gate electrode layers. A vertical insulating layer extends from the interlayer insulating layer disposed between the plurality of channel regions and the plurality of cell contact plugs and has a portion surrounded by at least one of the plurality of gate electrode layers. ## Claims ### Claim 1 A manufacturing method for memory device, comprising: forming a stack on a substrate, the stack including a plurality of insulating layers and a plurality of sacrificial layers stacked alternatively; forming a trench by removing a portion of the stack from an upper surface of the stack; forming a mask pattern on the stack; trimming the mask pattern by using the trench as a reference position; and forming at least one pad region by removing a portion of the stack exposed by the mask pattern. ### Claim 2 (depends on 1) The manufacturing method for memory device of claim 1, wherein a depth of the trench is greater than a sum of a thickness of an uppermost insulating layer among the plurality of insulating layers and a thickness of an uppermost sacrificial layer among the plurality of sacrificial layers. ### Claim 3 (depends on 1) The manufacturing method for memory device of claim 1, wherein a length of the at least one pad region in a first direction parallel to an upper surface of the substrate, is determined by an area trimmed in the mask pattern. ### Claim 4 (depends on 3) The manufacturing method for memory device of claim 3, wherein the area trimmed in the mask pattern is adjust by using the trench as the reference position, to determine the length of the at least one pad region. ### Claim 5 (depends on 1) The manufacturing method for memory device of claim 1, wherein the trench is filled with a same material with the mask pattern. ### Claim 6 (depends on 1) The manufacturing method for memory device of claim 1, further comprising: forming a mask layer having an open region corresponding to the trench, on the stack; and forming the trench by etching an area exposed by the open region. ### Claim 7 (depends on 1) The manufacturing method for memory device of claim 1, wherein the mask pattern has a quadrangular shape. ### Claim 8 (depends on 7) The manufacturing method for memory device of claim 7, wherein a length of the mask pattern in a first direction in which the mask pattern is trimmed is less than a width of the mask pattern in a second direction intersecting the first direction. ### Claim 9 (depends on 1) The manufacturing method for memory device of claim 1, wherein the trench is provided as a plurality of trenches, and the plurality of trenches are disposed along a second direction intersecting a first direction in which the mask pattern is trimmed. ### Claim 10 (depends on 1) The manufacturing method for memory device of claim 1, further comprising: forming a common source line and an isolation insulating layer dividing the stack into a plurality of unit regions. ### Claim 11 (depends on 10) The manufacturing method for memory device of claim 10, wherein the trench is provided as a plurality of trenches, and the number of the plurality of trenches is less than or equal to the number of the plurality of unit regions. ### Claim 12 (depends on 10) The manufacturing method for memory device of claim 10, wherein a width of the trench is less than ½ of the width of each of the plurality of unit regions. ### Claim 13 (depends on 1) The manufacturing method for memory device of claim 1, wherein trimming of the mask pattern and removing the portion of the stack exposed by the mask pattern are repeated a plurality of times to form a plurality of pad regions, and a length of each of the plurality of pad regions are determined by trimming the mask pattern by using the trench as the reference position, while the plurality of pad regions is formed. ### Claim 14 (depends on 1) The manufacturing method for memory device of claim 1, further comprising: forming a dummy trench between a first region, in which the stack is formed, and a second region peripheral to the first region, before forming the stack. ### Claim 15 The manufacturing method for memory device, comprising: forming a plurality of insulating layers and a plurality of sacrificial layers alternatively stacked on a substrate; forming a trench by removing a portion of an uppermost insulating layer among the plurality of insulating layers and a portion of an uppermost sacrificial layer among the plurality of sacrificial layers; forming a mask pattern on the plurality of insulating layers and the plurality of sacrificial layers to fill the trench; and forming a plurality of pad regions by repeating a step of trimming the mask pattern with reference to the trench and a step of removing at least a portion of the plurality of insulating layers and the plurality of sacrificial layers exposed by the mask pattern.