# US 10,373,973 B2 · Method of manufacturing semiconductor device through by-product removal from conductive layer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,973 B2 - Document ID: US10373973B2 - Status: Granted - Kind: B2 - Application number: 15/961,143 - Filed: 2018-04-24 - Published: 2019-03-14 - Granted: 2019-08-06 - Earliest claimed: 2017-09-11 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Won Joon Choi; Min Sung Ko; Kyeong Bae Kim; Jong Gi Kim; Dong Sun Sheen; Jung Myoung Shim; Young Ho Yang; Hyeng Woo Eom; Kwang Wook Lee; Woo Jae Chung - Web page: https://patentgrep.com/patent/US10373973B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10D 64/037: {comprising charge-trapping insulators} - H10P 50/269: {pre- or post-treatments, e.g. anti-corrosion processes} - H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation} - H10P 50/667: {by liquid etching only} - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract The method of manufacturing a semiconductor device include: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with source gas; and performing an out-gassing process to remove the second by-product. ## Claims ### Claim 1 A method of manufacturing a semiconductor device, comprising: forming conductive patterns in interlayer spaces between interlayer insulating layers, the conductive patterns being separated from each other by a slit passing through the interlayer insulating layers, wherein the conductive patterns include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive patterns with a source gas; performing an out-gassing process to remove the second by-product; and filling the slit with a sealing insulating layer so that the conductive patterns are sealed in the interlayer spaces. ### Claim 2 (depends on 1) The method according to claim 1, wherein the forming of the conductive patterns separated from each other by the slit comprises: alternately stacking sacrificial layers and the interlayer insulating layers; forming the slit passing through the sacrificial layers and the interlayer insulating layers; removing the sacrificial layers through the slit to expose the interlayer spaces; and filling the interlayer spaces with a conductive layer through the slit. ### Claim 3 (depends on 2) The method according to claim 2, further comprising dividing the conductive layer into the conductive patterns by removing a portion of the conductive layer in the slit through a wet etching process. ### Claim 4 (depends on 3) The method according to claim 3, further comprising: forming a hole passing through the sacrificial layers and the interlayer insulating layers; and forming a channel layer in the hole. ### Claim 5 (depends on 2) The method according to claim 2, wherein the forming of the conductive layer comprises depositing a tungsten layer using a tungsten precursor. ### Claim 6 (depends on 2) The method according to claim 2, wherein the forming of the conductive layer is performed at a first temperature, and wherein the generating of the second by-product is performed at a second temperature higher than the first temperature. ### Claim 7 (depends on 1) The method according to claim 1, wherein the generating of the second by-product comprises: injecting the source gas; and performing a heat treatment process within a range from 500° C. to 800° C. ### Claim 8 (depends on 1) The method according to claim 1, wherein the source gas includes silane. ### Claim 9 (depends on 1) The method according to claim 1, wherein the source gas includes tris dimethylamino silane (TDMAS). ### Claim 10 (depends on 1) The method according to claim 1, wherein the second by-product includes any one of HF and SiF4. ### Claim 11 (depends on 1) The method according to claim 1, further comprising, before the generating of the second by-product, performing a pre-heat treatment process for removing some of the first by-product. ### Claim 12 (depends on 1) The method according to claim 1, wherein an inert purge gas is supplied during the removing of the second by-product. ### Claim 13 (depends on 1) The method according to claim 1, wherein the generating of the second by-product, the out-gassing process to remove the second by-product, and the forming of the sealing insulating layer are performed in an in-situ manner. ### Claim 14 (depends on 1) The method according to claim 1, wherein the sealing insulating layer is formed using the source gas. ### Claim 15 (depends on 1) The method according to claim 1, wherein the sealing insulating layer is formed of a silicon-based insulating layer. ### Claim 16 (depends on 1) The method according to claim 1, wherein the sealing insulating layer includes at least one of SiO2, SiXNy, SiXOyNZ, HfO2, Al2O3, ZrO2, HfON, HfSiO, HfSiON, AlON, ZrON, ZrSiO, ZrSiON, TiO2, TiON, and TaxOy. ### Claim 17 A method of manufacturing a semiconductor device, comprising: forming interlayer insulating layers penetrated by a slit and stacked and spaced apart from each other with an interlayer space interposed therebetween; depositing a conductive layer with which the interlayer space is filled, wherein the conductive layer is deposited at a first temperature; removing a portion of the conductive layer in the slit through an etching process such that the conductive layer remains as a conductive pattern within the interlayer space; reacting a first by-product remaining in the conductive pattern with a source gas at a second temperature higher than the first temperature to form a second by-product of a gas phase; and performing an out-gassing process to remove the second by-product. ### Claim 18 A method of manufacturing a semiconductor device, comprising: forming conductive layers in interlayer spaces between interlayer insulating layers, wherein the conductive layers include a first by-product; generating a second by-product of a gas phase by reacting the first by-product remaining in the conductive layers with a source gas; and performing an out-gassing process to remove the second by-product. ### Claim 19 (depends on 18) The method according to claim 18, wherein the conductive layers are separated from each other by a slit passing through the interlayer insulating layers.