# US 10,373,968 B2 · 3-D semiconductor device and method for manufacturing the same

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- Number: US 10,373,968 B2
- Document ID: US10373968B2
- Status: Granted
- Kind: B2
- Application number: 15/306,179
- Filed: 2014-07-10
- Published: 2017-02-16
- Granted: 2019-08-06
- Earliest claimed: 2014-04-24
- Assignees: Institute of Microelectronics, Chinese Academy of Sciences
- Applicants: Institute of Microelectronics, Chinese Academy of Sciences
- Inventors: Zongliang Huo
- Web page: https://patentgrep.com/patent/US10373968B2

## CPC

- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/687: {having more than two programming levels}
- H10D 30/689: {Vertical floating-gate IGFETs}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A 3-D semiconductor device comprising a plurality of memory cells and a plurality of selection transistors, each of said plurality of memory cells comprises: a channel layer, distributed along a direction perpendicular to the substrate surface; a plurality of inter-layer insulating layers and a plurality of gate stack structures, alternately laminating along the sidewall of the channel layer; a plurality of floating gates, located between the plurality of inter-layer insulating layers and the sidewall of the channel layer; a plurality of drains, located at the top of the channel layer; and a plurality of sources, located in the said substrate between two adjacent memory cells of the said plurality of memory cells.

## Claims

### Claim 1

A 3-D semiconductor device comprising a plurality of memory cells and a plurality of selection transistors, each of said plurality of memory cells comprises: a channel layer, distributed along a direction perpendicular to a substrate surface; a plurality of inter-layer insulating layers and a plurality of gate stack structures, alternately laminated along a sidewall of the channel layer; a plurality of floating gates, located between the plurality of inter-layer insulating layers and the sidewall of the channel layer; a plurality of drains, located at the top of the channel layer; and a source, located in the said substrate and between every two adjacent memory cells of the said plurality of memory cells; and further comprising a discrete floating gate spacer between each of the plurality of the floating gates and the channel layer.

### Claim 2 (depends on 1)

The 3-D semiconductor device of claim 1, wherein, the cross-sectional shape of the channel layer parallel to the substrate surface comprises geometric shapes selected from rectangular, square, diamond, circular, semi-circular, elliptical, triangular, pentagonal, hexagonal, octagonal and the combinations thereof, and includes those selected from solid geometry, hollow annular geometry, or a combination of a hollow annular peripheral layer and a central insulating layer as a result of revolution of the said geometric shapes.

### Claim 3 (depends on 1)

The 3-D semiconductor device of claim 1, wherein, each of said plurality of gate stack structures includes a gate dielectric layer and a gate conductive layer.

### Claim 4 (depends on 3)

The 3-D semiconductor device of claim 3, wherein, the gate dielectric layer further comprises a tunneling layer, a storage layer, and a barrier layer.

### Claim 5 (depends on 3)

The 3-D semiconductor device of claim 3, wherein, a barrier layer of nitride between the gate dielectric layer and the gate conductive layer is further included.

### Claim 6 (depends on 1)

The 3-D semiconductor device of claim 1, wherein, the plurality of floating gates comprise a monolayer or multilayer structure of floating gate material layer; the material of the floating gate material layer comprises semiconductor materials or conductive materials, or dielectric materials with charge trapping capability.

### Claim 7 (depends on 1)

The 3-D semiconductor device of claim 1, wherein, each top of the plurality of sources comprises a metal silicide.

### Claim 8 (depends on 1)

The 3-D semiconductor device of claim 1, wherein, said plurality of selection transistors may or may not include a floating gate.