# US 10,373,967 B2 · Memory cell, nonvolatile semiconductor storage device, and method for manufacturing nonvolatile semiconductor storage device

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- Number: US 10,373,967 B2
- Document ID: US10373967B2
- Status: Granted
- Kind: B2
- Application number: 15/578,413
- Filed: 2016-12-07
- Published: 2018-10-04
- Granted: 2019-08-06
- Earliest claimed: 2015-12-18
- Assignees: Floadia Corporation
- Applicants: Floadia Corporation
- Inventors: Daisuke Okada; Kazumasa Yanagisawa; Fukuo Owada; Shoji Yoshida; Yasuhiko Kawashima; Shinji Yoshida; Yasuhiro Taniguchi; Kosuke Okuyama
- Web page: https://patentgrep.com/patent/US10373967B2

## CPC

- H10B 41/30: characterised by the memory core region
- G11C 16/04: using variable threshold transistors, e.g. FAMOS
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/30: characterised by the memory core region
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/68: Floating-gate IGFETs
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- G11C 16/02: electrically programmable
- G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors}
- G11C 16/10: Programming or data input circuits
- H10B 41/10: characterised by the top-view layout
- H10B 43/10: characterised by the top-view layout
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.

## Claims

### Claim 1

A memory cell comprising:
a semiconductor substrate covered by an insulating layer;
a fin disposed on the semiconductor substrate and protruding from the insulating layer;
a memory gate structure including a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a memory gate electrode stacked, and being disposed on the insulating layer so as to extend over the fin;
a first select gate structure including a first select gate electrode stacked on a first select gate insulating film, and being disposed on the insulating layer so as to extend over the fin along a first sidewall spacer disposed on one sidewall of the memory gate structure;
a second select gate structure including a second select gate electrode stacked on a second select gate insulating film, and being disposed on the insulating layer so as to extend over the fin along a second sidewall spacer disposed on the other sidewall of the memory gate structure;
a drain region provided adjacent to the first select gate structure on a surface of the fin, insulated from the first select gate electrode, and electrically connected with a bit line; and
a source region provided adjacent to the second select gate structure on the surface of the fin, insulated from the second select gate electrode, and electrically connected with a source line, wherein
the first select gate structure, the memory gate structure, and the second select gate structure are provided between the drain region and the source region, and
a thickness of the insulating layer between an upper surface of the semiconductor substrate and a lower surface of the lower memory gate insulating film is greater than thicknesses of the insulating layer between the upper surface of the semiconductor substrate and lower surfaces of the first and second select gate insulating films.

### Claim 2 (depends on 1)

The memory cell according to claim 1, wherein the insulating layer includes:
a layered insulating layer provided on the semiconductor substrate, and
a convex portion insulating layer provided in a region in which the memory gate structure is provided on the layered insulating layer.

### Claim 3 (depends on 2)

The memory cell according to claim 2, wherein the convex portion insulating layer has a thickness equal to or larger than a half of a width of the fin in a direction in which the memory gate structure, the first select gate structure, and the second select gate structure extend over the fin.

### Claim 4 (depends on 1)

The memory cell according to claim 1, wherein the memory gate electrode, the first select gate electrode, and the second select gate electrode contain metallic material.

### Claim 5 (depends on 1)

The memory cell according to claim 1, wherein the first select gate electrode is sidewall-shaped along the first sidewall spacer, and the second select gate electrode is sidewall-shaped along the second sidewall spacer.

### Claim 6 (depends on 1)

A nonvolatile semiconductor storage device comprising a plurality of memory cells arranged in a matrix of rows and columns and each including a memory gate electrode connected with a memory gate line, wherein each memory cell is the memory cell according to claim 1, and the memory gate line is shared by the memory cells arranged in the matrix.