# US 10,373,966 B2 · Mask ROM and process for fabricating the same

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- Number: US 10,373,966 B2
- Document ID: US10373966B2
- Status: Granted
- Kind: B2
- Application number: 15/264,423
- Filed: 2016-09-13
- Published: 2018-03-15
- Granted: 2019-08-06
- Earliest claimed: 2016-09-13
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Po-Han Jen; Chieh-Yu Tsai; Chun-Cheng Chiang
- Web page: https://patentgrep.com/patent/US10373966B2

## CPC

- H10B 20/38: {Doping programmed, e.g. mask ROM}
- H10D 1/47: Resistors having no potential barriers
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A Mask ROM is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-Si layer including an upper horizontal bar, a lower horizontal bar contiguous with the upper horizontal bar, and a step structure with a step height at which the two bars are contiguous, a spacer on the sidewall of the step structure, and a first silicide layer on the first poly-Si layer and being divided apart by the spacer. Each second resistor includes an undoped second poly-Si layer, and a contiguous second silicide layer on the second poly-Si layer. The contact plugs are disposed on the first silicide layer on the upper horizontal bar of each first poly-Si layer, and on the second silicide layer.

## Claims

### Claim 1

A Mask ROM, comprising:
a plurality of first resistors as a first part of memory cells, each of which includes:
an undoped first poly-Si layer including: an upper horizontal bar, a step structure with a step height, and a lower horizontal bar that is contiguous with the upper horizontal bar at the step structure and has a top surface being lower than a top surface of the upper horizontal bar by the step height and at same height as a bottom surface of the upper horizontal bar, wherein the step structure belongs to a portion of both the upper horizontal bar and the lower horizontal bar,
a spacer directly contacting on a sidewall of the upper horizontal bar and a portion of the top surface of the lower horizontal bar, and
a first silicide layer on the undoped first poly-Si layer, wherein the first silicide layer is divided apart by the spacer to be non-contiguous, and a height of the upper horizontal bar is smaller than the step height by a thickness of the first silicide layer;
a plurality of second resistors as a second part of the memory cells, each of which includes an undoped second poly-Si layer and a contiguous second silicide layer on the undoped second poly-Si layer; and
a plurality of contact plugs, disposed on the first silicide layer on the upper horizontal bar of each undoped first poly-Si layer, and on the second silicide layer.

### Claim 2 (depends on 1)

The Mask ROM of claim 1, wherein each first resistor further includes a material layer that is under the upper horizontal bar of the undoped first poly-Si layer and causes the step height.

### Claim 3 (depends on 2)

The Mask ROM of claim 2, wherein the material layer comprises an insulating layer.

### Claim 4 (depends on 3)

The Mask ROM of claim 3, wherein the insulating layer comprises a pad oxide layer and an SiN layer on the pad oxide layer.

### Claim 5 (depends on 1)

The Mask ROM of claim 1, wherein first portions of the second silicide layer and the first silicide layer on the lower horizontal bars of the undoped first poly-Si layers are connected with a plurality of word lines, and second portions of the second silicide layer and the first silicide layer on the upper horizontal bars of the undoped first poly-Si layers are connected with a plurality of bit lines.

### Claim 6 (depends on 1)

The Mask ROM of claim 1, wherein the first resistors and the second resistors are disposed on a field oxide (FOX) layer.

### Claim 7 (depends on 1)

The Mask ROM of claim 1, wherein the first resistors and the second resistors are disposed on a semiconductor substrate and separated from the semiconductor substrate by an insulating layer.

### Claim 8 (depends on 7)

The Mask ROM of claim 7, wherein the insulating layer is formed simultaneously with gate dielectric of logic devices.

### Claim 9 (depends on 1)

The Mask ROM of claim 1, wherein the undoped first poly-Si layers and the undoped second poly-Si layers are formed simultaneously with poly-Si gate electrodes of logic devices.

### Claim 10 (depends on 1)

The Mask ROM of claim 1, wherein the step height ranges from 300 Å to 500 Å.

### Claim 11

A Mask ROM, comprising:
a plurality of first resistors as a first part of memory cells, each of which includes:
an undoped first poly-Si layer including: an upper horizontal bar, a step structure with a step height, and a lower horizontal bar that is contiguous with the upper horizontal bar at the step structure and has a top surface being lower than a top surface of the upper horizontal bar by the step height and at same height as a bottom surface of the upper horizontal bar, wherein the step structure belongs to a portion of both the upper horizontal bar and the lower horizontal bar,
a first spacer directly contacting on a sidewall of the upper horizontal bar and a portion of the top surface of the lower horizontal bar, and a second spacer on a sidewall of the lower horizontal bar, and
a first silicide layer on the upper horizontal bar and the lower horizontal bar of the undoped first poly-Si layer, wherein the first silicide layer is divided apart by the first spacer to be non-contiguous, and a height of the upper horizontal bar is smaller than the step height by a thickness of the first silicide layer;
a plurality of second resistors as a second part of the memory cells, each of which includes an undoped second poly-Si layer and a contiguous second silicide layer on the undoped second poly-Si layer; and
a plurality of contact plugs, disposed on the first silicide layer on the upper horizontal bar of each undoped first poly-Si layer, and on the second silicide layer.