# US 10,373,964 B2 · Method of writing to memory circuit using resistive device

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- Number: US 10,373,964 B2
- Document ID: US10373964B2
- Status: Granted
- Kind: B2
- Application number: 15/864,873
- Filed: 2018-01-08
- Published: 2018-05-10
- Granted: 2019-08-06
- Earliest claimed: 2016-01-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yen-Huei Chen; Hung-Jen Liao; Chih-Yu Lin; Jonathan Tsung-Yung Chang; Wei-Cheng Wu
- Web page: https://patentgrep.com/patent/US10373964B2

## CPC

- H10B 10/15: {comprising a resistor load element}
- G11C 11/412: using field-effect transistors only
- G11C 11/419: Read-write [R-W] circuits
- H10D 1/00: Resistors, capacitors or inductors
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4441: {the principal metal being a refractory metal}
- H10W 20/498: {Resistive arrangements or effects of, or between, wiring layers}
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method, of writing to a memory cell, includes: causing a pulling device of the memory cell to pull a voltage level at a first data node of the memory cell toward a first supply voltage level responsive to a voltage level at a second data node of the memory cell; causing a pass gate of the memory cell to pull the voltage level at the first data node of the memory cell toward a second supply voltage level responsive to a word line signal, the second supply voltage level being different from the first supply voltage level; and limiting a driving capability of the pulling device by a resistive device, the resistive device being electrically coupled between the pulling device and a supply voltage source configured to provide a first supply voltage, the first supply voltage having the first supply voltage level.

## Claims

### Claim 1

A method of writing to a memory cell, comprising:
causing a pulling device of the memory cell to pull a voltage level at a first data node of the memory cell toward a first supply voltage level responsive to a voltage level at a second data node of the memory cell;
causing a pass gate of the memory cell to pull the voltage level at the first data node of the memory cell toward a second supply voltage level responsive to a word line signal, the second supply voltage level being different from the first supply voltage level; and
limiting a driving capability of the pulling device by a resistive device, the resistive device being electrically coupled between the pulling device and a supply voltage source configured to provide a first supply voltage, the first supply voltage having the first supply voltage level.

### Claim 2 (depends on 1)

The method of writing to a memory cell of claim 1, wherein:
the pass gate is an N-type transistor;
the pulling device is a P-type transistor; and
setting the first supply voltage level to be greater than the second supply voltage level.

### Claim 3 (depends on 1)

The method of writing to a memory cell of claim 1, wherein:
the pass gate is a P-type transistor;
the pulling device is an N-type transistor; and
setting the second supply voltage level to be greater than the first supply voltage level.

### Claim 4 (depends on 1)

The method of writing to a memory cell of claim 1, wherein:
the pulling device is coupled to a first conductive segment in a first conductive layer of the memory cell;
the supply voltage source is coupled to a second conductive segment in a second conductive layer of the memory cell;
a via layer is disposed between the first and second conductive layers;
the via layer includes first-type vias and second-type vias, each of the first-type vias having a first resistance value, each of the second-type vias having a second resistance value, and the second resistance value being substantially greater than the first resistance value; and
the limiting a driving capability of the pulling device includes:
using at least one of the first-type vias to couple the first conductive segment in the first conductive layer to the second conductive segment in the second conductive layer.

### Claim 5 (depends on 1)

The method of writing to a memory cell of claim 1, wherein the limiting a driving capability of the pulling device includes:
using a passive device as the resistive device.

### Claim 6 (depends on 1)

The method of writing to a memory cell of claim 1, wherein the limiting a driving capability of the pulling device includes:
using an active device as the resistive device.

### Claim 7 (depends on 6)

The method of writing to a memory cell of claim 6, wherein the using an active device includes:
using a transistor in an always-on configuration as the active device.

### Claim 8 (depends on 1)

The method of writing to a memory cell of claim 1, wherein:
the pulling device is located in a first layer of a memory device; and
the limiting a driving capability of the pulling device includes:
using a device in a second layer of the memory cell as the resistive device.

### Claim 9 (depends on 8)

The method of writing to a memory cell of claim 8, wherein:
the second layer is a via layer; and
the using a device in a second layer of the memory cell as the resistive device includes:
using a via in the via layer as the resistive device.

### Claim 10

A method of writing to a memory cell, comprising:
turning on a pulling device of the memory cell and thereby pulling a voltage level at a first data node of the memory cell toward a first supply voltage level;
the pulling device being coupled to a first conductive segment in a first conductive layer of the memory cell;
a source of the first supply voltage level being coupled to a second conductive segment in a second conductive layer of the memory cell;
turning on a pass gate of the memory cell and thereby pulling the voltage level at the first data node of the memory cell toward a second supply voltage level, the second supply voltage level being different from the first supply voltage level; and
weakening a driving capability of the pulling device;
wherein:
the memory cell includes a via layer is disposed between the first and second conductive layers;
the via layer includes first-type vias and second-type vias, each of the first-type vias having a first resistance value, each of the second-type vias having a second resistance value, and the second resistance value being substantially greater than the first resistance value; and
the weakening includes:
using at least one of the first-type vias to couple the first conductive segment in the first conductive layer to the second conductive segment in the second conductive layer.

### Claim 11 (depends on 10)

The method of writing to a memory cell of claim 10, wherein:
the pass gate is an N-type transistor;
the pulling device is a P-type transistor; and
setting the first supply voltage level to be greater than the second supply voltage level.

### Claim 12 (depends on 10)

The method of writing to a memory cell of claim 10, wherein:
the pass gate is a P-type transistor;
the pulling device is an N-type transistor; and
setting the second supply voltage level to be greater than the first supply voltage level.

### Claim 13 (depends on 10)

The method of writing to a memory cell of claim 10, wherein:
the first-type vias are formed of a material which includes at least one of Copper or Aluminum.

### Claim 14 (depends on 10)

The method of writing to a memory cell of claim 10, wherein:
the second-type vias are formed of a material which includes at least one of Tungsten, Cobalt, polysilicon or a doped semiconductor.

### Claim 15 (depends on 10)

The method of writing to a memory cell of claim 10, wherein:
each of the second-type vias has a length, relative to a first direction, which is greater than a length of each of the first-type vias.

### Claim 16

A method of writing to a memory cell, comprising:
turning on a pulling device of the memory cell and thereby pulling a voltage level at a first data node of the memory cell toward a first supply voltage level;
turning on a pass gate of the memory cell and thereby pulling the voltage level at the first data node of the memory cell toward a second supply voltage level, the second supply voltage level being different from the first supply voltage level; and
weakening a driving capability of the pulling device;
wherein:
the pulling device is located in a first layer of a memory device; and
the weakening includes:
using, in order to couple the pulling device and a source of the first supply voltage level, a conductive path which includes a resistive device, the resistive device being is located in a second layer of the memory cell.

### Claim 17 (depends on 16)

The method of writing to a memory cell of claim 16, wherein the weakening includes:
using a passive device as the resistive device.

### Claim 18 (depends on 16)

The method of writing to a memory cell of claim 16, wherein the weakening includes:
using an active device as the resistive device.

### Claim 19 (depends on 18)

The method of writing to a memory cell of claim 18, wherein the using an active device includes:
using a transistor in an always-on configuration as the active device.

### Claim 20 (depends on 16)

The method of writing to a memory cell of claim 16, wherein:
the resistive device is formed of a material which includes at least one of Tungsten, Cobalt, polysilicon or a doped semiconductor; and
other portions of the conductive path are formed of corresponding materials each of which includes at least one of Copper or Aluminum.