# US 10,373,963 B2 · Method for fabricating a local interconnect in a semiconductor device

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- Number: US 10,373,963 B2
- Document ID: US10373963B2
- Status: Granted
- Kind: B2
- Application number: 15/986,312
- Filed: 2018-05-22
- Published: 2018-09-20
- Granted: 2019-08-06
- Earliest claimed: 2015-12-03
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jui-Yao Lai; Sai-Hooi Yeong; Yen-Ming Chen; Ying-Yan Chen; Jeng-Ya David Yeh
- Web page: https://patentgrep.com/patent/US10373963B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/853: {comprising FinFETs}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 95/06: {Planarisation of inorganic insulating materials}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device comprises a first gate electrode disposed on a substrate, a first source/drain region, and a local interconnect connecting the first gate electrode and the first source/drain region. The local interconnect is disposed between the substrate and a first metal wiring layer in which a power supply line is disposed. The local interconnect has a key hole shape in a plan view, and has a head portion, a neck portion and a body portion connected to the head portion via the neck portion. The neck portion is disposed over the first gate electrode and the body portion is disposed over the first source/drain region.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a first gate structure and a second gate structure over a substrate, the first gate structure including a first gate electrode, a first cap insulating layer disposed over the first gate electrode and a first sidewall spacer disposed on side faces of the first gate electrode and the first cap insulating layer, the second gate structure including a second gate electrode, a second cap insulating layer disposed over the second gate electrode and a second sidewall spacer disposed on side faces of the second gate electrode and the second cap insulating layer;
forming a first source/drain region in an area between the first sidewall spacer and the second sidewall spacer;
forming a first insulating layer over the first source/drain region and between the first sidewall spacer and the second sidewall spacer;
after forming the first insulating layer, removing a part of the first cap insulating layer, thereby forming a first space;
forming a second insulating layer over the first and second gate structures and in the first space;
removing a part of the second insulating layer and a part of the first insulating layer above the first source/drain region, and further removing a part of the first sidewall spacer, thereby forming a second space in which a part of an upper surface of the first gate electrode and the first source/drain region are exposed; and
filling the second space with a conductive material, thereby connecting the first gate electrode and the first source/drain region.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the first and second insulating layers are made of silicon oxide, and
the first and second cap insulating layers include at least one selected from the group consisting of SiN, SiCN, SiON and SiOCN.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first and second sidewall spacers are made of a different material than the first and second cap insulating layers.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first and second sidewall spacers include at least one selected from the group consisting of SiN, SiCN, SiON and SiOCN.

### Claim 5 (depends on 1)

The method of claim 1, wherein the conductive material is made of at least one selected from the group consisting of W and Co.

### Claim 6 (depends on 1)

The method of claim 1, wherein the filling the second space with a conductive material includes:
forming a blanket layer of the conductive material; and
performing a planarization operation such that an upper surface of the first cap insulating layer, an upper surface of the first sidewall spacer and an upper surface of the filled conductive material are flush with each other.

### Claim 7 (depends on 1)

The method of claim 1, wherein, after the first space is formed and before the second insulating layer is formed, an uppermost portion of the first sidewall spacer is higher than an uppermost portion of the first gate electrode.

### Claim 8 (depends on 1)

The method of claim 1, wherein, after the conductive material is formed, an uppermost portion of the first sidewall spacer is higher than an uppermost portion of the first gate electrode.

### Claim 9 (depends on 8)

The method of claim 8, wherein:
after the first space is formed and before the second insulating layer is formed, an uppermost portion of the first sidewall spacer is higher than an uppermost portion of the first gate electrode, and
the height of the uppermost portion of the first sidewall spacer after the conductive material is formed is lower than the height of the uppermost portion of the first sidewall spacer after the first space is formed and before the second insulating layer is formed.

### Claim 10 (depends on 1)

The method of claim 1, wherein:
the removing the part of the first cap insulating layer includes:
forming a mask pattern having an opening over the first cap insulating layer; and
etching the part of the first cap insulating layer through the opening, and
the opening partially overlaps the first sidewall spacer.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first sidewall spacer is partially etched during the etching the part of the first cap insulating layer.

### Claim 12 (depends on 10)

The method of claim 10, wherein the opening partially does not overlap the first source/drain region.

### Claim 13 (depends on 1)

The method of claim 1, wherein:
the removing the part of the second insulating layer and the part of the first insulating layer and the removing the part of the first sidewall spacer includes:
forming a mask pattern having an opening over the first space filled with the second insulating layer and the first source/drain region; and
etching the part of the second insulating layer, the part of the first insulating layer and the part of the first sidewall spacer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the opening is further over the second sidewall spacer and the second cap insulating layer.

### Claim 15 (depends on 13)

The method of claim 13, wherein the opening only partially overlaps with the first space filled with the second insulating layer.

### Claim 16 (depends on 1)

The method of claim 1, wherein:
the conductive material connecting the first gate electrode and the first source/drain region has a key hole shape in a plan view, and has a head portion, a neck portion and a body portion connected to the head portion via the neck portion,
the head portion is disposed over and in contact with the first gate electrode,
the body portion is disposed over and in contact with the first source/drain region and is in contact with the first and second sidewall spacers, and
a width of the neck portion measured in a first direction in which the first and second gate electrode extend in plan view is smaller than a width of the head portion and a width of the body portion, in plan view, the first direction being perpendicular to a second direction in which the first gate electrode, the first source/drain region and the second gate electrode are arranged in this order.

### Claim 17

A method of manufacturing a static random access memory (SRAM) cell, the SRAM cell comprising:
a first field effect transistor (FET) having a first gate, a first source and a first drain, the first gate being coupled to a word line, the first drain being coupled to a first bit line;
a second FET having a second gate, a second source and a second drain, the second drain being coupled to a first power supply line;
a third FET having a third gate, a third source and a third drain, the third drain being coupled to a second power supply line;
a fourth FET having a fourth gate, a fourth source and a fourth drain, the fourth gate being coupled to the word line, and the fourth drain being coupled to a second bit line;
a fifth FET having a fifth gate, a fifth source and a fifth drain, the fifth drain being coupled to the first power supply line;
a sixth FET having a sixth gate, a sixth source and a sixth drain, the sixth drain being coupled to the second power supply line, wherein:
the second gate and the third gate share a first gate electrode layer and the fifth gate and the sixth gate share a second gate electrode layer,
the method comprising:
forming a first epitaxial layer over the first source and the second source, and a second epitaxial layer over the third source; and
forming a first local interconnect that electrically connects the first epitaxial layer, the second epitaxial layer and the second gate electrode layer,
wherein a portion of the first local interconnect connecting the second epitaxial layer and the second gate electrode layer has a neck portion having a width narrower than a head portion of the first local interconnect disposed over the second gate electrode layer, in a direction in which the second gate electrode extends.

### Claim 18 (depends on 17)

The method of claim 17, further comprising forming a first sidewall spacer on a side face of the first gate electrode layer,
wherein the neck portion is disposed over the first sidewall spacer.

### Claim 19 (depends on 18)

The method of claim 18, further comprising forming a first cap insulating layer over the first gate electrode layer,
wherein the head portion is in contact with the first cap insulating layer.

### Claim 20

A method of manufacturing a semiconductor device, the method comprising:
forming a first gate structure and a second gate structure over a substrate, the first gate structure including a first gate electrode, a first cap insulating layer disposed over the first gate electrode and a first sidewall spacer disposed on side faces of the first gate electrode and the first cap insulating layer, the second gate structure including a second gate electrode, a second cap insulating layer disposed over the second gate electrode and a second sidewall spacer disposed on side faces of the second gate electrode and the second cap insulating layer;
forming a first source/drain region and a second source/drain region in an area between the first sidewall spacer and the second sidewall spacer;
forming a first insulating layer over the first and second source/drain regions and between the first sidewall spacer and the second sidewall spacer;
after forming the first insulating layer, removing a part of the first cap insulating layer, thereby forming a first space adjacent to the first source/drain region with the first sidewall spacer interposed;
forming a second insulating layer over the first and second gate structures and in the first space;
removing a part of the second insulating layer and a part of the first insulating layer above the first and second source/drain regions, and further removing a part of the first sidewall spacer adjacent to the firs source/drain region, thereby forming a second space in which a part of an upper surface of the first gate electrode and the first source/drain region are exposed and a third space in which the first source/drain region are exposed; and
filling the second space and the third with a conductive material, thereby connecting the first gate electrode and the first source/drain region, and forming a contact layer over the second source/drain region.