Semiconductor memory devices including separate upper and lower bit line spacers
AssigneeSamsung Electronics Co., Ltd.
InventorsDaeik Kim, Semyeong Jang, Jemin Park, Yoosang Hwang
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Abstract
A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.
Claims21
A volatile memory device comprising:
- a bit line structure having a vertical side wall;
- a lower spacer on a lower portion of the vertical side wall, wherein the lower spacer is defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer;
- and
- an upper spacer on an upper portion of the vertical side wall above the lower portion, wherein the upper spacer is defined by a second thickness from the vertical side wall to an outer side wall of the upper spacer, wherein the second thickness is less than the first thickness, and wherein the upper spacer exposes an uppermost portion of the outer side wall of the lower spacer,
- wherein the lower spacer comprises:
- a first sub-spacer;
- and
- a second sub-spacer on the first sub-spacer, wherein an uppermost surface of the first sub-spacer is partially covered by a lowest surface of the upper spacer to leave a portion of the uppermost surface of the first sub-spacer exposed.
The volatile memory device of claim l, further comprising:
- a storage node contact plug;
- and
- a landing pad on the storage node contact plug, wherein the lower portion of the vertical side wall comprises a level at an uppermost surface of the storage node contact plug and a level at a lowest surface of the landing pad.
A volatile memory device comprising:
- a bit line structure comprising a bit line contact plug, a bit line metal-containing pattern, and a bit line capping pattern stacked on one another;
- a storage node contact plug in a storage node contact hole adjacent to the bit line structure;
- a lower spacer comprising a first sub-spacer and a second sub-spacer on the first sub-spacer, wherein the first sub-spacer and the second sub-spacer have a combined thickness, wherein the lower spacer is on a vertical side wall of the bit line structure to provide a side wall of the storage node contact hole, and wherein the lower spacer has an uppermost surface comprising respective portions of the first and second sub-spacers;
- and
- an upper spacer having an upper thickness that is less than the combined thickness of the first sub-spacer and the second sub-spacer, wherein the upper spacer has a lowest surface that terminates at the uppermost surface to cover a portion of the uppermost surface and to expose a remaining portion of the uppermost surface, and wherein an outer side wall of the lower spacer extends further from the vertical side wall of the bit line structure than an outer side wall of the upper spacer extends from the vertical side wall of the bit line structure.
Dependencies are inferred from the claim text.