# US 10,373,959 B2 · Semiconductor memory device and method of fabricating the same

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- Number: US 10,373,959 B2
- Document ID: US10373959B2
- Status: Granted
- Kind: B2
- Application number: 16/050,848
- Filed: 2018-07-31
- Published: 2019-03-21
- Granted: 2019-08-06
- Earliest claimed: 2017-09-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dong-Hyun Im; Daehyun Kim; Hoon Park; Jae-Hong Seo; Chunhyung Chung; Jae-Joong Choi
- Web page: https://patentgrep.com/patent/US10373959B2

## CPC

- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 64/027: {by etching at gate locations}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P 14/40: of conductive or resistive materials
- H10D 64/01304: {characterised by the conductor}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.

## Claims

### Claim 1

A method of fabricating a semiconductor memory device, comprising:
etching a substrate wherein a trench is formed that crosses active regions of the substrate;
forming a gate insulating layer on bottom and side surfaces of the trench;
forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench;
oxidizing a top surface of the first gate electrode wherein a preliminary barrier layer is formed;
nitrifying the preliminary barrier layer wherein a barrier layer is formed; and
forming a second gate electrode on the barrier layer that fills an upper portion of the trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein nitrifying the preliminary barrier layer nitrifies an exposed portion of the gate insulating layer located above the first gate electrode.

### Claim 3 (depends on 1)

The method of claim 1, wherein nitrifying the preliminary barrier layer nitrifies an upper portion of the first gate electrode.

### Claim 4 (depends on 1)

The method of claim 1, wherein
oxidizing the top surface of the first gate electrode injects oxygen atoms into the first gate electrode, and
nitrifying the preliminary barrier layer injects nitrogen atoms into crystalline defects of the preliminary barrier layer.

### Claim 5 (depends on 1)

The method of claim 1, further comprising etching the gate insulating layer before forming the second gate electrode, wherein a thickness of a portion of the gate insulating layer exposed above the barrier layer is reduced.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first gate electrode comprises a first metal, and
the barrier layer comprises an oxynitride of the first metal.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming a liner layer that covers a top surface of the barrier layer and a side surface of the gate insulating layer exposed above the barrier layer, before forming the second gate electrode.

### Claim 8 (depends on 1)

The method of claim 1, further comprising forming a capping layer on the second gate electrode that fills a remaining region of the trench.

### Claim 9

A semiconductor memory device, comprising:
a semiconductor substrate that includes a trench;
a gate insulating layer disposed in the trench that covers bottom and inner side surfaces of the trench;
a first gate electrode disposed in a lower portion of the trench, the first gate electrode including a first metal;
a second gate electrode disposed in the trench and on the first gate electrode; and
a barrier layer disposed between the first and second gate electrodes, the barrier layer including an oxynitride of the first metal,
wherein the second gate electrode has a work-function that is less than the work-function of the first gate electrode.

### Claim 10 (depends on 9)

The device of claim 9, wherein the gate insulating layer has a first portion adjacent to the first gate electrode and a second portion adjacent to the second gate electrode, and
when measured in a direction perpendicular to a side surface of the trench, the first portion is thicker than the second portion.

### Claim 11 (depends on 10)

The device of claim 10, wherein a thickness of the first portion is about 40% to 70% greater than a thickness of the second portion.

### Claim 12 (depends on 9)

The device of claim 9, wherein the second gate electrode is wider than the first gate electrode.

### Claim 13 (depends on 9)

The device of claim 9, wherein a nitrogen concentration of a portion of the gate insulating layer adjacent to the second gate electrode is greater than the nitrogen concentration of a portion of the gate insulating layer adjacent to the first gate electrode.

### Claim 14 (depends on 9)

The device of claim 9, wherein a thickness of the barrier layer ranges from 1 Å to 30 Å.

### Claim 15 (depends on 9)

The device of claim 9, wherein the second gate electrode comprises poly-silicon doped with n-type impurities.

### Claim 16 (depends on 9)

The device of claim 9, wherein the first gate electrode and the second gate electrode are spaced apart from each other by the barrier layer.

### Claim 17 (depends on 9)

The device of claim 9, further comprising a liner layer disposed between the barrier layer and the second gate electrode,
wherein the liner layer extends into a space between the gate insulating layer and the second gate electrode.

### Claim 18 (depends on 9)

The device of claim 9, wherein the substrate further comprises:
active regions surrounded by a device isolation layer, wherein the active regions extend in a direction that crosses the trenches; and
doped regions formed in the active regions,
wherein the doped regions comprise first doped regions disposed between the trenches, and second doped regions disposed between the trenches and the device isolation layer.

### Claim 19 (depends on 18)

The device of claim 18, further comprising
bit lines disposed on the substrate and connected to the first doped regions; and
capacitors disposed on the substrate and connected to the second doped regions.

### Claim 20

A semiconductor memory device, comprising:
a substrate that includes active regions surrounded by a device isolation layer, the active regions extending in a first direction;
gate lines buried in trenches formed in an upper portion of the substrate, wherein the gate lines cross the active regions in a second direction that crosses the first direction and divide the active regions into first and second doped regions; and
a bit line disposed on the gate lines that extends in a third direction that crosses both of the first and second directions,
wherein each of the gate lines comprises:
a first gate electrode disposed in a lower portion of the trench, wherein a top surface of the first gate electrode includes oxygen and nitrogen atoms; and
a second gate electrode disposed on the first gate electrode.