# US 10,373,958 B2 · Semiconductor device having a multi-thickness gate trench dielectric layer

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- Number: US 10,373,958 B2
- Document ID: US10373958B2
- Status: Granted
- Kind: B2
- Application number: 15/876,216
- Filed: 2018-01-22
- Published: 2019-01-31
- Granted: 2019-08-06
- Earliest claimed: 2017-07-31
- Assignees: United Microelectronics Corp.; Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicants: United Microelectronics Corp.; Fujian Jinhua Integrated Circuit Co., Ltd.
- Inventors: Tsuo-Wen Lu; Ger-Pin Lin; Tien-Chen Chan; Shu-Yen Chan
- Web page: https://patentgrep.com/patent/US10373958B2

## CPC

- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10D 30/0225: {using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/027: {by etching at gate locations}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10D 64/01346: {in a gaseous ambient using an oxygen or a water vapour, e.g. oxidation through a layer (H10D64/01344 takes precedence)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate having a gate trench including an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate having a gate trench comprised of an upper trench and a lower trench, wherein the upper trench is wider than the lower trench;
a gate embedded in the gate trench, wherein the gate comprises an upper portion and a lower portion;
a first gate dielectric layer between the upper portion and the upper trench, wherein the first gate dielectric layer has a first thickness; and
a second gate dielectric layer between the lower portion and the lower trench, wherein the second gate dielectric layer has a second thickness that is smaller than the first thickness, wherein the gate comprises a tungsten layer and TiN liner layer, wherein the TiN liner layer is disposed between the tungsten layer and the first gate dielectric layer and between the tungsten layer and the second gate dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the gate has a uniform width throughout depth of the gate trench.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the upper portion of the gate has a width that is equal to that of the lower portion of the gate.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the gate trench has a trench width gradually decreased from its top to its bottom.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the first gate dielectric layer comprises an atomic layer deposition (ALD) silicon oxide layer.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the first thickness ranges between 60 and 80 angstroms.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the second gate dielectric layer comprises an in-situ steam generation (ISSG) silicon oxide layer.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the second thickness ranges between 40 and 60 angstroms.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the first gate dielectric layer comprises a surface that is aligned with a surface of the second gate dielectric layer.