Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors

A memory array, comprising:

• a series of access lines;
• a series of bitlines;
• a plurality of gated bipolar junction transistors, individual gated bipolar junction transistors comprised by the plurality of gated bipolar junction transistors each being uniquely addressed through combinations containing a single bitline comprised by the series of bitlines and a single access line comprised by the series of access lines, each of the individual gated bipolar junction transistors comprising:
• a vertical transistor pillar having a pair of opposing sidewalls, the pair of opposing sidewalls including a first sidewall and a second sidewall, the vertical transistor pillar having a base region between a pair of emitter/collector regions, one of the pair of emitter/collector regions being a first emitter/collector region and the other being a second emitter/collector region, the first emitter/collector region interfacing the base region at a first junction and the second emitter/collector region interfacing the base region at a second junction, the first emitter/collector region being directly electrically coupled with the single bitline;
• a first depletion region disposed at an interface of the base region and the first emitter/collector region, and a second depletion region disposed at an interface of the base region and the second emitter/collector region, the first depletion region and the second depletion region each comprising a silicon carbide material having a bandgap greater than or equal to 1.2 eV at 300 K, at least a portion of vertical transistor pillar comprising a non silicon carbide material having narrow bandgap;
• and
• a gate along the base region of the vertical transistor pillar, the gate not vertically overlapping either of the first junction and the second junction;
• and
• a dielectric material extending along an entirety of a vertical height of each of the first sidewall and the second sidewall of the vertical transistor pillar, a portion of the dielectric material along the first depletion region comprising silicon, oxygen and nitrogen.