# US 10,373,955 B2 · Semiconductor device with FIN transistors and manufacturing method of such semiconductor device

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- Number: US 10,373,955 B2
- Document ID: US10373955B2
- Status: Granted
- Kind: B2
- Application number: 15/588,072
- Filed: 2017-05-05
- Published: 2017-08-24
- Granted: 2019-08-06
- Earliest claimed: 2010-10-29
- Assignees: Sony Corporation
- Applicants: Sony Corporation
- Inventors: Koichi Matsumoto
- Web page: https://patentgrep.com/patent/US10373955B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/0132: {the conductor being a metallic silicide}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/668: {the layer being a silicide, e.g. TiSi2}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 64/675: {Gate sidewall spacers}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0179: {the gate conductors having different shapes or dimensions}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device including: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes agate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor base; and
a first conductivity type transistor and a second conductivity type transistor on the semiconductor base, the second conductivity type being opposite that of the first conductivity type,
wherein,
(a) each of the first conductivity type transistor and the second conductivity type transistor includes
a high dielectric gate insulating film on the base, the high dielectric gate insulating film having a dielectric constant higher than that of silicon oxide,
a metal gate electrode on the gate insulating film, and
side wall spacers at side walls of the metal gate electrode, and
(b) each of the first conductivity type transistor and the second conductivity type transistor further includes offset spacers on the gate insulating film and between the side walls of the metal gate electrode and the side wall spacers.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein each of the first conductivity type transistor and the second conductivity type transistor includes a work function layer between the gate insulating layer and the metal gate electrode.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first conductivity type transistor has raised source and drain regions that extend above a top surface of the semiconductor base.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein, for both the first and second conductivity transistors, the side wall spacers are at sides of both the gate insulating film and the work function layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a cross sectional width of the metal gate electrode of the first conductivity type transistor is less than that of the second conductivity type transistor.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the metal gate electrodes are made of a pure metal or an alloy of a pure metal.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the metal gate electrodes are made of Ti, Al, Cu, W, or an alloy including one of the metals.

### Claim 8 (depends on 2)

The semiconductor device of claim 2, wherein the work function layer of the first conductivity type transistor is made of (a) alloy including Ru, Pd, Pt, Co, Ni, or Mo, (b) an oxide, or (c) TiN; and the work function layer of the second conductivity type transistor is made of (a) alloys including Hf, Zr, Ti, Ta, or Al, (b) a carbide, or (c) HfSi.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the gate insulating layers are made of a material selected from the group consisting of HfO, HfSiO, LaO, ZrO, ZrSiO, TaO, TiO, BaSrTiO, BaTiO, StTiO, YO, AlO, and PbScTaO.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, further comprising, raised source/drain portions formed of epitaxial layers on the base directly under the side wall spacers.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the first conductivity type transistor and second conductivity type transistor are buried in an interlayer insulating layer.