# US 10,373,953 B2 · Semiconductor device including a semiconductor extension layer between active regions

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- Number: US 10,373,953 B2
- Document ID: US10373953B2
- Status: Granted
- Kind: B2
- Application number: 15/159,464
- Filed: 2016-05-19
- Published: 2016-11-24
- Granted: 2019-08-06
- Earliest claimed: 2015-05-19
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sungmin Kim; Jisu Kang; Jaehyun Park; Heonjong Shin; Yuri Lee
- Web page: https://patentgrep.com/patent/US10373953B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other, an isolation pattern disposed between the first and second active regions, a semiconductor extension layer disposed between the first and second active regions, a first source/drain semiconductor layer disposed on the first active region, and a second source/drain semiconductor layer disposed on the second active region. The facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.

## Claims

### Claim 1

A semiconductor device, comprising:
a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other;
an isolation pattern disposed between the first and second active regions;
a semiconductor extension layer disposed between the first and second active regions;
a first source/drain semiconductor layer disposed on the first active region; and
a second source/drain semiconductor layer disposed on the second active region;
wherein the semiconductor extension layer is disposed between the first active region and the isolation pattern and between the second active region and the isolation pattern.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor extension layer is in contact with the side surfaces of the first and second active regions.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a level of an upper end of the semiconductor extension layer is higher than a level of an upper surface of the isolation pattern relative to the semiconductor substrate.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor extension layer extends under the isolation pattern relative to the semiconductor substrate.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first source/drain semiconductor layer is disposed in a first recessed area in the first active region.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein a level of an upper end of the semiconductor extension layer is higher than a level of a bottom of the first recessed area relative to the semiconductor substrate.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein a level of a bottom of the semiconductor extension layer is lower than a level of a bottom of the first recessed area relative to the semiconductor substrate.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein:
the semiconductor extension layer is a first epitaxial layer; and
the first and second source/drain semiconductor layers are second epitaxial layers different from the first epitaxial layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.

### Claim 10

A semiconductor device, comprising:
a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other;
an isolation pattern disposed between the first and second active regions;
a semiconductor extension layer disposed between the first and second active regions;
a first source/drain semiconductor layer disposed on the first active region; and
a second source/drain semiconductor layer disposed on the second active region;
wherein the first source/drain semiconductor layer is disposed in a first recessed area in the first active region; and
wherein a level of an upper end of the semiconductor extension layer is higher than a level of a bottom of the first recessed area relative to the semiconductor substrate.

### Claim 11

A semiconductor device, comprising:
a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other;
an isolation pattern disposed between the first and second active regions;
a semiconductor extension layer disposed between the first and second active regions;
a first source/drain semiconductor layer disposed on the first active region; and
a second source/drain semiconductor layer disposed on the second active region;
wherein the first source/drain semiconductor layer is disposed in a first recessed area in the first active region; and
wherein a level of a bottom of the semiconductor extension layer is lower than a level of a bottom of the first recessed area relative to the semiconductor substrate.