# US 10,373,950 B2 · Super CMOS devices on a microelectronics system

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- Number: US 10,373,950 B2
- Document ID: US10373950B2
- Status: Granted
- Kind: B2
- Application number: 15/799,921
- Filed: 2017-10-31
- Published: 2018-06-28
- Granted: 2019-08-06
- Earliest claimed: 2008-12-23
- Assignees: Schottky Lsi, Inc.
- Applicants: Schottky Lsi, Inc.
- Inventors: Augustine Wei-Chun Chang
- Web page: https://patentgrep.com/patent/US10373950B2

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables
- H10B 12/50: {Peripheral circuit region structures}
- H10B 20/00: Read-only memory [ROM] devices
- H10B 20/38: {Doping programmed, e.g. mask ROM}
- H10B 20/60: {Peripheral circuit regions}
- H10B 20/65: {of memory structures of the ROM only type}
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/49: comprising different types of peripheral transistor
- H10D 8/051: {of Schottky diodes}
- H10D 8/60: Schottky-barrier diodes
- H10D 84/0165: {the components including complementary IGFETs, e.g. CMOS devices}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/907: {CMOS gate arrays}
- H10D 89/10: Integrated device layouts
- H10F 10/16: Photovoltaic cells having only PN heterojunction potential barriers
- H10F 10/164: comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
- H10F 10/18: Photovoltaic cells having only Schottky potential barriers
- H10F 77/12: Active materials
- H10F 77/166: Amorphous semiconductors
- H10F 77/1662: {including only Group IV materials}
- H10W 90/00: Package configurations
- H10D 1/47: Resistors having no potential barriers
- Y02E 10/50: Photovoltaic [PV] energy
- Y02E 10/548: Amorphous silicon PV cells
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10B: ELECTRONIC MEMORY DEVICES
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION

## Abstract

A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P— and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

## Claims

### Claim 1

An electronic system, comprising:
a substrate;
a first transistor device formed on the substrate, wherein the first transistor device has a diffusion bed; and
a first Schottky barrier diode (SBD) formed on the substrate, wherein the first SBD is attached to the diffusion bed of the first transistor device and includes a metal barrier contact to the diffusion bed of the first transistor device, wherein the first SBD and the first transistor device are isolated from other semiconductor devices on the substrate via an isolation trench.

### Claim 2 (depends on 1)

The electronic system of claim 1, wherein the first SBD includes a p-type SBD.

### Claim 3 (depends on 1)

The electronic system of claim 1, wherein the first SBD includes an n-type SBD.

### Claim 4 (depends on 1)

The electronic system of claim 1, wherein the first transistor device includes one of metal oxide field effect transistor device (MOSFET), a bipolar junction transistor device (BJT) and a multi-level cell FLASH transistor.

### Claim 5 (depends on 4)

The electronic system of claim 4, wherein the first transistor device is based on at least one of Silicon (Si), Silicon-Germanium (SiGe), Gallium Arsenide (GaAs), Gallium Nitride (GaN), Indium Phosphide (InP), and other III-V Compound Semiconductor materials and combination thereof.

### Claim 6 (depends on 5)

The electronic system of claim 5, wherein the first SBD has a substantially low threshold voltage that is no greater than 0.5V.

### Claim 7 (depends on 1)

The electronic system of claim 1, wherein the metal barrier contact of the first SBD is made of Co/Ti.

### Claim 8 (depends on 1)

The electronic system of claim 1, further comprising a second SBD formed on the substrate, wherein the second SBD is attached to a diffusion bed of a second transistor device that is distinct from the first transistor device.

### Claim 9 (depends on 8)

The electronic system of claim 8, wherein the first and second SBDs are complementary to each other.

### Claim 10 (depends on 1)

The electronic system of claim 1, wherein the first SBD and the first transistor device are disposed in a semiconductor well on the substrate.

### Claim 11 (depends on 1)

The electronic system of claim 1, wherein the substrate includes a sub-implant layer that is buried underneath the first SBD, and the first transistor device does not lie on top of the sub-implant layer.

### Claim 12 (depends on 1)

The electronic system of claim 1, wherein the isolation trench is filled with oxide.

### Claim 13 (depends on 1)

The electronic system of claim 1, wherein the SBD includes a low barrier SBD.

### Claim 14 (depends on 1)

The electronic system of claim 1, wherein the first SBD includes a cathode, an anode, and a blockout region disposed on top of one of the cathode and the anode.

### Claim 15 (depends on 1)

The electronic system of claim 1, wherein the diffusion bed of the first transistor device includes a drain of the first transistor.

### Claim 16 (depends on 15)

The electronic system of claim 15, wherein the first transistor device and the first SBD are configured to implement at least one of a memory, a solar concentrator, a pass transistor device logic, an amplifier, a HI-Z block, a Schmitt trigger, an RFID circuit, a high-frequency timing block, and a memory peripheral.

### Claim 17 (depends on 1)

The electronic system of claim 1, wherein the first transistor device occupies a first area of the substrate, and the first SBD occupies a second area of the substrate that is substantially smaller than the first area of the substrate.

### Claim 18 (depends on 1)

The electronic system of claim 1, wherein the first transistor device includes a gate surrounded by a layer of tunnel oxide.

### Claim 19 (depends on 18)

The electronic system of claim 18, wherein the thickness of the layer of tunnel oxide is substantially equal to or less than 10 nm.

### Claim 20 (depends on 1)

The electronic system of claim 1, wherein the substrate is made of (i) one of silicon single crystal, amorphous silicon, glass, GaAs, or other semiconductor compound material, and (ii) a metal panel.