# US 10,373,949 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 10,373,949 B2
- Document ID: US10373949B2
- Status: Granted
- Kind: B2
- Application number: 15/677,190
- Filed: 2017-08-15
- Published: 2018-08-23
- Granted: 2019-08-06
- Earliest claimed: 2017-02-20
- Assignees: Mediatek Inc.
- Applicants: MEDIATEK Inc.
- Inventors: Yan-Liang Ji; Cheng-Hua Lin; Chih-Chung Chiu
- Web page: https://patentgrep.com/patent/US10373949B2

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/80: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence)
- H10W 20/43: Layouts of interconnections
- H10D 1/47: Resistors having no potential barriers
- H10D 84/40: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate and a passive component. The passive component is formed on the semiconductor substrate and includes a first polysilicon (poly) layer, a salicide blockage (SAB) layer and a first salicide layer. The SAB layer is formed on the first poly layer. The first salicide layer is formed on the SAB layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate; and
a passive component formed on the semiconductor substrate and comprising:
a first polysilicon (poly) layer;
a salicide blockage (SAB) layer formed on the first poly layer; and
a first salicide layer covering the entire upper surface of the SAB layer.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a first contact formed on a first upper surface of the first salicide layer and electrically connecting to a controller, wherein the controller is configured to provide the passive component with a constant voltage.

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a first contact formed on the first salicide layer and electrically connecting to a controller, wherein the controller is configured to provide the passive component with a controllable voltage.

### Claim 4 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first poly layer has a second upper surface and a first lateral surface and a second lateral surface opposite to the first lateral surface, and the SAB layer covers a portion of the second upper surface, a portion of the first lateral surface and a portion of the second lateral surface.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first poly layer has a third lateral surface and a fourth lateral surface opposite to the third lateral surface, and the SAB layer exposes the third lateral surface and a fourth lateral surface.

### Claim 6 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a first contact formed on the first salicide layer covering the SAB layer.

### Claim 7 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a second contact formed on the first salicide layer covering the first poly layer.

### Claim 8 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first salicide layer includes a first salicide portion and a second salicide portion, and the first salicide portion formed on the SAB layer is separated from the second salicide portion formed on the first poly layer by a third lateral surface of the SAB layer.

### Claim 9 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first poly layer has a second upper surface, the SAB layer covers a first portion of the second upper surface and exposes a second portion of the second upper surface, and the first salicide layer is formed on the entire upper surface of the SAB layer and the second portion.

### Claim 10 (depends on 1)

The semiconductor device as claimed in claim 1, further comprises:
a metal-oxide-semiconductor (MOS);
a second salicide layer formed on the MOS; and
a third salicide layer formed on the semiconductor substrate;
wherein the first salicide layer, the second salicide layer and the third salicide layer are the same layer structure formed in the same process.

### Claim 11 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first salicide layer is formed by reacting a second poly layer with a reaction layer.

### Claim 12

A semiconductor device, comprising:
a semiconductor substrate; and
a passive component formed on the semiconductor substrate and comprising:
a first polysilicon (poly) layer;
a salicide blockage (SAB) layer formed on the first poly layer; and
a first salicide layer formed on the SAB layer;
wherein the first poly layer has two terminal portions projected with respect to two lateral surfaces of the SAB layer respectively.