# US 10,373,948 B2 · On-die system electrostatic discharge protection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,948 B2 - Document ID: US10373948B2 - Status: Granted - Kind: B2 - Application number: 15/203,296 - Filed: 2016-07-06 - Published: 2018-01-11 - Granted: 2019-08-06 - Earliest claimed: 2016-07-06 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Christopher P. Mozak; Victor Zia; Gabriel J. Thompson - Web page: https://patentgrep.com/patent/US10373948B2 ## CPC - H10D 89/817: {FETs in a Darlington configuration} - H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits} - H10D 89/611: {using diodes as protective elements} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) ## Abstract Some embodiments include apparatus and methods using a first transistor coupled between a node and a supply node, a second transistor coupled between the node and a ground node, an electrostatic discharge (ESD) protection unit including a diode coupled between the node and an additional node, and a transistor coupled between the additional node and the supply node. ## Claims ### Claim 1 An apparatus comprising: a first transistor coupled between a node and a supply node, the first transistor including a gate; a second transistor coupled between the node and a ground node, the second transistor including a gate coupled to the gate of the first transistor; an electrostatic discharge (ESD) protection unit including a diode coupled between the node and an additional node; a transistor coupled between the additional node and the supply node; a first additional transistor, wherein the transistor and the first additional transistor are coupled in parallel with each other between the additional node and the supply node; and a second additional transistor coupled in series with the first additional transistor between the additional node and the supply node the second additional transistor including a gate coupled to a node between the first additional transistor and the second additional transistor. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the ESD protection unit includes a transistor coupled between the additional node and the ground node. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the ESD protection unit includes an RC tuner to control the transistor coupled between the additional node and the ground node. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the RC timer includes a resistor, and a capacitor coupled to a terminal of the resistor, and the ESD protection unit includes an additional transistor coupled between the terminal of the resistor and the ground node. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the ESD protection unit includes an additional diode coupled between the node and the ground node. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the apparatus comprises an integrated circuit chip, wherein the first transistor, the second transistor, the ESD protection unit, and the transistor coupled between the additional node and the supply node are located on a die of the integrated circuit chip. ### Claim 7 An apparatus comprising: an input/output (I/O) node, a supply node, and a ground node; a driver circuit including a first transistor coupled between the I/O node and the supply node, and a second transistor coupled between the I/O node and the ground node, the first transistor including a gate coupled to a gate of the second transistor; an electrostatic discharge (ESD) protection unit including a first diode coupled between the I/O node and the ground node, a second diode coupled between the I/O node and an additional node, a clamp circuit coupled between the additional node and the ground node, and a clamp control circuit coupled to the clamp circuit; and a coupling circuit coupled between the additional node and the supply node including: a transistor coupled between the additional node and the supply node; a first additional transistor, wherein the transistor and the first additional transistor are coupled in parallel with each other between the additional node and the supply node; and a second additional transistor coupled in series with the first additional transistor between the additional node and the supply node, the second additional transistor including a gate coupled to a node between the first additional transistor and the second additional transistor, wherein the ESD protection unit further includes a third diode and a fourth diode coupled between the additional node and the ground node, wherein: the first diode includes an anode coupled to the ground node, and a cathode coupled to the I/O node; the second diode includes an anode coupled to the I/O node, and a cathode coupled to the additional node; the third diode includes an anode coupled to the ground node; and the fourth diode includes a cathode coupled to the additional node. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the clamp circuit includes at least one transistor coupled between the additional node and the ground node. ### Claim 9 (depends on 7) The apparatus of claim 7, wherein the clamp control circuit includes an RC timer to provide a signal at a timer node between a resistor of the RC timer a capacitor of the RC timer. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the clamp circuit is to turn on during an ESD event, and the clamp control circuit is to discharge the timer node when the clamp circuit is turned on. ### Claim 11 (depends on 7) The apparatus of claim 7, wherein the driver circuit includes an additional transistor having a gate to receive a signal from the I/O node. ### Claim 12 (depends on 7) The apparatus of claim 7, wherein the coupling circuit is to cause the additional node to have a voltage having a first value based on a first operating mode of the apparatus, and to cause the additional node to have a voltage having a second value based on a second operating mode of the apparatus. ### Claim 13 An apparatus comprising: a first input/output (I/O) node; a second I/O node; a first clamp circuit to turn on and form a circuit path between the first I/O node and a ground node during an electrostatic discharge (ESD) event occurred at the first I/O node; a second clamp circuit to turn on and form a circuit path between the second I/O node and the ground node during the ESD event; and a clamp control circuit to turn off the first and second clamp circuits at different times after the first and second clamp circuits are turned on. ### Claim 14 (depends on 13) The apparatus of claim 13, further comprising: a third I/O node; a third clamp circuit to turn on and form a circuit path between the third I/O node and the ground node during the ESD event, wherein the clamp control circuit is to turn off the third clamp circuit after the third clamp circuit is turned on and after first and second clamp circuits are turned off. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein each of the first, second, and third clamp circuits includes a logic gate, the logic gate including an input node coupled to receive a signal from the clamp control circuit. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the logic gate of the first clamp circuit includes an output node coupled to an input node of the logic gate of the second clamp circuit, and the logic gate of the second clamp circuit includes an output node coupled to an input node of the logic gate of the third clamp circuit. ### Claim 17 (depends on 13) The apparatus of claim 13, further comprising a coupling circuit, the coupling circuit including at least one transistor coupled between the clamp control circuit and a supply node. ### Claim 18 An apparatus comprising: a first integrated circuit (IC) chip on a circuit board; a second IC chip on the circuit board and coupled to the first IC chip, at least one of the first and second IC chips including a processor; and at least one of the first and second IC chips including: a first transistor coupled between a node and a supply node, the first transistor including a gate; a second transistor coupled between the node and a ground node, the second transistor including a gate coupled to the gate of the first transistor; an electrostatic discharge (ESD) protection unit including a diode coupled between the node and an additional node; a transistor coupled between the additional node and the supply node; a first additional transistor, wherein the transistor and the first additional transistor are coupled in parallel with each other between the additional node and the supply node; and a second additional transistor coupled in series with the first additional transistor between the additional node and the supply node, the second additional transistor including a gate coupled to a node between the first additional transistor and the second additional transistor; and a connector coupled to at least one of the first and second IC chips. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the connector conforms with one of Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), and Ethernet specifications.