# US 10,373,943 B2 · Semiconductor device

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- Number: US 10,373,943 B2
- Document ID: US10373943B2
- Status: Granted
- Kind: B2
- Application number: 15/953,899
- Filed: 2018-04-16
- Published: 2018-11-01
- Granted: 2019-08-06
- Earliest claimed: 2017-04-28
- Assignees: Socionext Inc.
- Applicants: Socionext Inc.
- Inventors: Hirotaka Takeno; Atsushi Okamoto
- Web page: https://patentgrep.com/patent/US10373943B2

## CPC

- H10D 89/10: Integrated device layouts
- H03K 17/161: {in field-effect transistor switches}
- H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/853: {comprising FinFETs}
- H10D 84/907: {CMOS gate arrays}
- H10W 20/427: {Power or ground buses}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/975: {Wiring regions or routing}
- H10D 84/981: {Power supply lines}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third power supply line, a fourth power supply line coupled to the second circuit, a first switch circuit including a first switch transistor and a well tap, the first switch transistor including one source or drain end coupled to the first power supply line and another source or drain end coupled to the second power supply line, the well tap being electrically coupled to the second power supply line, and a second switch circuit including a second switch transistor including one source or drain end coupled to the third power supply line and another source or drain end coupled to the fourth power supply line, the second switch circuit including no well tap electrically coupled to the fourth power supply line.

## Claims

### Claim 1

A semiconductor device, comprising:
a first circuit formed in a semiconductor substrate;
a second circuit formed in the semiconductor substrate;
a first power supply line;
a second power supply line coupled to the first circuit;
a first ground line;
a third power supply line;
a fourth power supply line coupled to the second circuit;
a second ground line;
a first switch circuit including a first switch transistor and a well tap of the semiconductor substrate, the first switch transistor including a first source and a first drain, one of the first source and the first drain being coupled to the first power supply line, another of the first source and the first drain being coupled to the second power supply line, and the well tap being electrically coupled to the second power supply line; and
a second switch circuit including a second switch transistor, the second switch transistor including a second source and a second drain, one of the second source and the second drain being coupled to the third power supply line, another of the second source and the second drain being coupled to the fourth power supply line, the second switch circuit including no well tap of the semiconductor substrate electrically coupled to the fourth power supply line.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the second power supply line, the fourth power supply line, the first ground line, and the second ground line extend in a first direction, and a length of the second switch circuit in the first direction is shorter than a length of the first switch circuit in the first direction.

### Claim 3 (depends on 2)

The semiconductor device as claimed in claim 2, wherein
the first switch circuit is located alongside the first circuit, and
the second switch circuit is located alongside the second circuit.

### Claim 4 (depends on 2)

The semiconductor device as claimed in claim 2, wherein
the semiconductor device includes a plurality of the second switch circuits,
the plurality of the second switch circuits are arranged alongside the second circuit, and
the second switch circuits are aligned in a second direction perpendicular to the first direction.

### Claim 5 (depends on 2)

The semiconductor device as claimed in claim 2, wherein
the semiconductor device includes a plurality of the second circuits, and
the second switch circuit is located between two of the second circuits in a plan view.

### Claim 6 (depends on 2)

The semiconductor device as claimed in claim 2, wherein
the fourth power supply line and the second ground line are terminated at an edge of a design area which includes the first circuit and the second circuit, and
the second switch circuit is located between the edge of the design area and the second circuit.

### Claim 7 (depends on 2)

The semiconductor device as claimed in claim 2, wherein the second switch circuit include end-cap areas arranged alongside the second switch transistor on respective sides of the second switch transistor in the first direction.

### Claim 8 (depends on 2)

The semiconductor device as claimed in claim 2, wherein
a second circuit includes a terminal electrically coupled to the first circuit,
the terminal is located at a first side of the second circuit, and
the second switch circuit is located alongside a second side of the second circuit which is opposite to the first side.

### Claim 9 (depends on 2)

The semiconductor device as claimed in claim 2, wherein
the first power supply line bifurcates in the first switch circuit in a plan view,
the second power supply line bifurcates in the first switch circuit in a plan view,
the first power supply line is coupled to one of the first source and the first drain of the first switch transistor via a plurality of first contacts which are formed on the semiconductor substrate,
the second power supply line is coupled to another of the first source and the first drain of the first switch transistor via a plurality of second contacts which are formed on the semiconductor substrate,
the third power supply line bifurcates in the second switch circuit in a plan view,
the fourth power supply line bifurcates in the second switch circuit in a plan view,
the third power supply line is coupled to one of the second source and the second drain of the second switch transistor via a plurality of third contacts which are formed on the semiconductor substrate, and
the fourth power supply line is coupled to another of the second source and the second drain of the second switch transistor via a plurality of fourth contacts which are formed on the semiconductor substrate.

### Claim 10 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the first switch transistor and the second switch transistor have the same structure.