# US 10,373,940 B2 · Stacked semiconductor package

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,373,940 B2
- Document ID: US10373940B2
- Status: Granted
- Kind: B2
- Application number: 15/806,618
- Filed: 2017-11-08
- Published: 2018-05-10
- Granted: 2019-08-06
- Earliest claimed: 2016-11-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dong-ha Lee
- Web page: https://patentgrep.com/patent/US10373940B2

## CPC

- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 74/014: {using batch processing}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07354: {changes in dispositions}
- H10W 72/075: {of bond wires}
- H10W 72/07554: {changes in dispositions}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a stacked semiconductor package, which has various kinds of semiconductor chips with various sizes and is capable of miniaturization. The stacked semiconductor package includes a base substrate layer and a sub semiconductor package disposed on a top surface of the base substrate layer. The sub semiconductor package includes a plurality of sub semiconductor chips spaced apart from one another, and a sub mold layer filling spaces between the plurality of sub semiconductor chips to surround side surfaces of the plurality of sub semiconductor chips. The stacked semiconductor package includes at least one main semiconductor chip stacked on the sub semiconductor package, the at least one main semiconductor chip being electrically connected to the base substrate layer through first electrical connection members.

## Claims

### Claim 1

A stacked semiconductor package comprising:
a base substrate layer;
a sub semiconductor package disposed on a top surface of the base substrate layer, the sub semiconductor package comprising:
a plurality of sub semiconductor chips spaced horizontally apart from one another,
a sub mold layer filling spaces between the plurality of sub semiconductor chips to surround side surfaces of the plurality of sub semiconductor chips, and
a redistribution structure provided on active surfaces of the plurality of sub semiconductor chips and on the sub mold layer, the redistribution structure comprising redistribution pads electrically connected to the base substrate layer and a redistribution conductive layer configured to connect at least some of the plurality of sub semiconductor chips with the redistribution pads; and
at least one main semiconductor chip stacked on the sub semiconductor package, the at least one main semiconductor chip electrically connected to the base substrate layer through first electrical connection members.

### Claim 2 (depends on 1)

The stacked semiconductor package of claim 1, wherein the sub semiconductor package has the same area from a plan view as each main semiconductor chip of the at least one main semiconductor chip.

### Claim 3 (depends on 2)

The stacked semiconductor package of claim 2, wherein the sub semiconductor package is adhered to the top surface of the base substrate layer such that active surfaces of the plurality of sub semiconductor chips face away from the base substrate layer,
the stacked semiconductor package further comprising second electrical connection members electrically connecting the redistribution pads with the base substrate layer,
wherein the first electrical connection members and the second electrical connection members are bonding wires.

### Claim 4 (depends on 3)

The stacked semiconductor package of claim 3, wherein the redistribution pads do not overlap at least a first main semiconductor chip of the at least one main semiconductor chip in a direction perpendicular to a main surface of the base substrate layer.

### Claim 5 (depends on 2)

The stacked semiconductor package of claim 2, wherein the at least one main semiconductor chip includes a plurality of main semiconductor chips stacked in a staircase form, and the first electrical connection members are bonding wires.

### Claim 6 (depends on 5)

The stacked semiconductor package of claim 5, wherein a lowermost main semiconductor chip of the plurality of main semiconductor chips overlaps the sub semiconductor package in a direction perpendicular to a main surface of the base substrate layer.

### Claim 7 (depends on 6)

The stacked semiconductor package of claim 6, further comprising:
second electrical connection members electrically connecting the redistribution pads with the base substrate layer; and
a die bonding film between the sub semiconductor package and the lowermost main semiconductor chip,
wherein the second electrical connection members are bonding wires, and
the die bonding film buries portions of the second electrical connection members.

### Claim 8 (depends on 6)

The stacked semiconductor package of claim 6, wherein the lowermost main semiconductor chip is stacked on the sub semiconductor package in a staircase form.

### Claim 9 (depends on 1)

The stacked semiconductor package of claim 1, wherein the sub semiconductor package has the same thickness in a vertical direction as at least a first main semiconductor chip of the at least one main semiconductor chip.

### Claim 10

A stacked semiconductor package comprising:
a sub semiconductor package comprising a plurality of sub semiconductor chips spaced horizontally apart from one another, a sub mold layer filling spaces between the plurality of sub semiconductor chips, and a redistribution structure including redistribution pads and a redistribution conductive layer configured to connect at least some of the plurality of sub semiconductor chips with the redistribution pads, the redistribution structure being on active surfaces of the plurality of sub semiconductor chips and on the sub mold layer; and
a plurality of main semiconductor chips, each of which has the same area as the sub semiconductor package, the plurality of main semiconductor chips being stacked on the sub semiconductor package in a staircase form.

### Claim 11 (depends on 10)

The stacked semiconductor package of claim 10, wherein each semiconductor chip of the plurality of main semiconductor chips has an area when viewed from a top down view larger than that of each sub semiconductor chip of the plurality of sub semiconductor chips.

### Claim 12 (depends on 10)

The stacked semiconductor package of claim 10, wherein a surface of the sub mold layer facing the redistribution structure is coplanar with the active surfaces of the plurality of sub semiconductor chips.

### Claim 13 (depends on 10)

The stacked semiconductor package of claim 10, further comprising a base substrate layer having a top surface to which the sub semiconductor package is adhered, wherein first top connection pads electrically connected to the sub semiconductor package and second top connection pads electrically connected to the plurality of main semiconductor chips are on the top surface of the base substrate layer,
wherein the first top connection pads and the second top connection pads are adjacent to different sides of the top surface of the base substrate layer.

### Claim 14

A stacked semiconductor package comprising:
a base package substrate;
a sub semiconductor package disposed on the base package substrate, the sub semiconductor package including:
a plurality of first semiconductor chips horizontally spaced apart from each other, at least two of which have different areas from each other, when viewed from a plan view;
a sub mold layer filling spaces between the first semiconductor chips; and
a sub package substrate disposed on the plurality of first semiconductor chips and the sub mold layer;
at least a second semiconductor chip disposed on the sub semiconductor package, the second semiconductor chip having a larger area than each first semiconductor chip of the plurality of first semiconductor chips, when viewed from a plan view; and
a mold layer covering the sub semiconductor package and the second semiconductor chip,
wherein the sub semiconductor package has the same area as the second semiconductor chip, when viewed from a plan view.

### Claim 15 (depends on 14)

The stacked semiconductor package of claim 14, wherein the sub package substrate is a redistribution structure including redistribution pads and a redistribution conductive layer configured to connect at least some of the plurality of first semiconductor chips with the redistribution pads.

### Claim 16 (depends on 15)

The stacked semiconductor package of claim 15, wherein the base package substrate includes top connection pads for connecting to the redistribution pads.

### Claim 17 (depends on 16)

The stacked semiconductor package of claim 16, wherein the base package substrate includes additional top connection pads for connecting to respective wire connection pads formed on the second semiconductor chip.

### Claim 18 (depends on 14)

The stacked semiconductor package of claim 14, wherein the sub semiconductor package is disposed between the base package substrate and the second semiconductor chip.

### Claim 19 (depends on 14)

The stacked semiconductor package of claim 14, further comprising:
a third semiconductor chip of the same type and size as the second semiconductor chip, stacked on the second semiconductor chip.

### Claim 20 (depends on 19)

The stacked semiconductor package of claim 19, wherein at least one of the second semiconductor chip and third semiconductor chip overhangs the sub semiconductor package.