# US 10,373,935 B2 · Semiconductor package

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- Number: US 10,373,935 B2
- Document ID: US10373935B2
- Status: Granted
- Kind: B2
- Application number: 16/114,795
- Filed: 2018-08-28
- Published: 2018-12-27
- Granted: 2019-08-06
- Earliest claimed: 2016-05-17
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sun-kyoung Seo; Cha-jea Jo; Soo-hyun Ha
- Web page: https://patentgrep.com/patent/US10373935B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 72/0198: {batch processes}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

## Claims

### Claim 1

A semiconductor package comprising:
a first semiconductor chip including a first through-electrode;
a plurality of second semiconductor chips stacked on a top surface of the first semiconductor chip, at least one of the plurality of second semiconductor chips including a second through-electrode;
a plurality of first connection bumps attached to a bottom surface of the first semiconductor chip, each of the plurality of first connection bumps comprising a first pillar structure and a first solder layer; and
a plurality of second connection bumps between the first semiconductor chip and a lowermost second semiconductor chip and between adjacent two second semiconductor chips among the plurality of second semiconductor chips, each of the plurality of second connection bumps comprising a second pillar structure and a second solder layer,
wherein the first pillar structure comprises a first pillar layer, a diffusion barrier layer, and an adhesive layer, and the second pillar structure comprises a second pillar layer and does not comprise a layer corresponding to the adhesive layer.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the first pillar layer, the diffusion barrier layer and the adhesive layer are sequentially stacked on the bottom surface of the first semiconductor chip.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein the first pillar layer comprises a material having a Young's modulus that is lower than a Young's modulus of the second pillar layer.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein the first pillar layer comprises copper (Cu), and the second pillar layer comprises nickel (Ni).

### Claim 5 (depends on 3)

The semiconductor package of claim 3, wherein the diffusion barrier layer comprises nickel (Ni).

### Claim 6 (depends on 3)

The semiconductor package of claim 3, wherein the adhesive layer comprises copper (Cu).

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein a height of the first connection bumps is higher than that of the second connection bumps.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein a diameter of the first pillar layer is smaller than that of the diffusion barrier layer.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein the first through-electrode is connected to one of the plurality of first connection bumps and to one of the plurality of second connection bumps.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, further comprising:
a first molding member surrounding side surfaces of the plurality of second semiconductor chips and the plurality of second connection bumps, the first molding member being not in contact with the bottom surface of the first semiconductor chip or the plurality of first connection bumps.

### Claim 11 (depends on 1)

The semiconductor package of claim 1, wherein the second solder layer comprises a material having a melting point higher than a melting point of the first solder layer.

### Claim 12 (depends on 1)

The semiconductor package of claim 1, further comprising:
a substrate facing the bottom surface of the first semiconductor chip and electrically connected to the first semiconductor chip through the plurality of first connection bumps; and
an external connection terminal on a bottom surface of the substrate opposite to a top surface of the substrate that faces the first semiconductor chip,
wherein a width of one of the plurality of first connection bumps in a second direction, which is parallel to the top surface of the first semiconductor chip, is smaller than a width of the external connection terminal in the second direction.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein the substrate is an interposer or a printed circuit board (PCB), and the width of the external connection terminal in the second direction is greater than 50 μm.

### Claim 14

A semiconductor package comprising:
a first semiconductor chip including a first through-electrode;
a plurality of second semiconductor chips stacked on a top surface of the first semiconductor chip, at least one of the plurality of second semiconductor chips including a second through-electrode;
a plurality of first connection bumps attached to a bottom surface of the first semiconductor, chip, each of the plurality of first connection bumps comprising a first pillar structure and a first solder layer, the first pillar structure including a first pillar layer and a diffusion barrier layer, a diameter of the first pillar layer being smaller than that of the diffusion barrier layer; and
a plurality of second connection bumps between the first semiconductor chip and a lowermost second semiconductor chip and between adjacent two second semiconductor chips among the plurality of second semiconductor chips, each of the plurality of second connection bumps comprising a second pillar structure and a second solder layer.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein the first solder layer includes tin (Sn) and copper (Cu), while the second solder layer includes tin (Sn) and does not includes copper (Cu).

### Claim 16 (depends on 15)

The semiconductor package of claim 15, wherein the first pillar structure include an intermediate layer which contacts the first solder layer, and the intermediate layer includes at least one of (Cu,Ni)6Sn5, (Cu,Ni)3Sn4, and (Cu,Ni)3Sn.

### Claim 17 (depends on 14)

The semiconductor package of claim 14, wherein a height of the first connection bumps is higher than that of the second connection bumps.

### Claim 18 (depends on 14)

The semiconductor package of claim 14, wherein a composition of the first solder layer is different from that of the second solder layer.

### Claim 19 (depends on 14)

The semiconductor package of claim 14, wherein the first through-electrode is connected to one of the plurality of first connection bumps and to one of the plurality of second connection bumps.

### Claim 20 (depends on 19)

The semiconductor package of claim 19, further comprising:
a substrate facing the bottom surface of the first semiconductor chip and electrically connected to the first semiconductor chip through the plurality of first connection bumps; and
an external connection terminal located on a bottom surface of the substrate opposite to a top surface of the substrate that faces the first semiconductor chip,
wherein a width of one of the plurality of first connection bumps in a second direction that is parallel to the top surface of the first semiconductor chip is smaller than a width of the external connection terminal in the second direction.