# US 10,373,932 B2 · Stacked semiconductor structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,932 B2 - Document ID: US10373932B2 - Status: Granted - Kind: B2 - Application number: 15/491,995 - Filed: 2017-04-20 - Published: 2018-10-25 - Granted: 2019-08-06 - Earliest claimed: 2017-04-20 - Assignees: Nanya Technology Corporation - Applicants: Nanya Technology Corporation - Inventors: Po-Chun Lin; Chin-Lung Chu - Web page: https://patentgrep.com/patent/US10373932B2 ## CPC - H10W 90/00: Package configurations - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/01: {Manufacture or treatment} - H10W 72/073: {of die-attach connectors} - H10W 72/07353: {changes in shapes} - H10W 72/334: {Cross-sectional shape, i.e. in side view} - H10W 72/834: {Interconnections on sidewalls of chips} - H10W 90/20: Configurations of stacked chips - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A stacked semiconductor structure is provided. The stacked semiconductor structure includes a substrate, a first electronic component, a first fillet, and a first redistribution layer. The substrate has a support surface. The substrate includes a first pad disposed on the support surface. The first electronic component is disposed on the support surface and has a first bottom surface, a first top surface, and a first side surface connecting the first bottom surface and the first top surface. The first electronic component includes a second pad disposed on the first top surface. The first fillet is disposed on the support surface and the first side surface and has a first inclined surface. The first redistribution layer is disposed on the support surface, the first top surface, and the first inclined surface and electrically connecting the first pad to the second pad. ## Claims ### Claim 1 A stacked semiconductor structure, comprising: a substrate having a support surface, wherein the substrate includes a first pad disposed on the support surface; a first electronic component disposed on the support surface and having a first bottom surface, a first top surface, and a first side surface connecting the first bottom surface and the first top surface, wherein the first electronic component includes a second pad disposed on the first top surface; a first fillet disposed on the support surface and the first side surface and having a first inclined surface; a first redistribution layer disposed on the support surface, the first top surface, and the first inclined surface and electrically connecting the first pad to the second pad; and a die attachment disposed between the support surface and the first bottom surface, wherein the die attachment and the first fillet are made of the same material. ### Claim 2 (depends on 1) The stacked semiconductor structure of claim 1, wherein the substrate further includes a body and at least one second redistribution layer disposed in the body. ### Claim 3 (depends on 1) The stacked semiconductor structure of claim 1, further comprising: a plurality of solder balls disposed on a surface of the substrate opposite to the support surface. ### Claim 4 (depends on 1) The stacked semiconductor structure of claim 1, further comprising: a package member disposed on the support surface and covering the first electronic component. ### Claim 5 (depends on 1) The stacked semiconductor structure of claim 1, wherein the first electronic component is a chip. ### Claim 6 (depends on 1) The stacked semiconductor structure of claim 1, wherein the first fillet covers the first side surface. ### Claim 7 (depends on 1) The stacked semiconductor structure of claim 1, wherein the first redistribution layer is further disposed on the first side surface. ### Claim 8 (depends on 1) The stacked semiconductor structure of claim 1, further comprising: a second electronic component disposed on the first top surface and having a second bottom surface, a second top surface, and a second side surface connecting the second bottom surface and the second top surface, wherein the second electronic component includes a third pad disposed on the second top surface; and a second fillet disposed on the second side surface and having a second inclined surface. ### Claim 9 (depends on 8) The stacked semiconductor structure of claim 8, wherein the second fillet is further disposed on the first top surface, and the first redistribution layer is further disposed on the second inclined surface and the second top surface and further electrically connected to the third pad. ### Claim 10 (depends on 8) The stacked semiconductor structure of claim 8, wherein the second fillet is further disposed on the first inclined surface; and further comprising: a second redistribution layer disposed on the second inclined surface and the second top surface and electrically connecting the first pad to the third pad. ### Claim 11 (depends on 10) The stacked semiconductor structure of claim 10, wherein the first redistribution layer is electrically connected to the second redistribution layer. ### Claim 12 (depends on 10) The stacked semiconductor structure of claim 10, wherein the first redistribution layer is electrically isolated from the second redistribution layer. ### Claim 13 (depends on 8) The stacked semiconductor structure of claim 8, wherein an orthogonal projection of the first electronic component on the substrate and an orthogonal projection of the second electronic component on the substrate are substantially the same. ### Claim 14 (depends on 8) The stacked semiconductor structure of claim 8, wherein a substantial portion of an orthogonal projection of the second electronic component on the substrate does not overlap with an orthogonal projection of the first electronic component on the substrate. ### Claim 15 (depends on 8) The stacked semiconductor structure of claim 8, wherein the second electronic component covers the second pad. ### Claim 16 (depends on 8) The stacked semiconductor structure of claim 8, wherein the second electronic component does not cover the second pad. ### Claim 17 (depends on 8) The stacked semiconductor structure of claim 8, wherein an orthogonal projection of the second pad on the substrate overlaps with an orthogonal projection of the second electronic component on the substrate. ### Claim 18 (depends on 8) The stacked semiconductor structure of claim 8, wherein an orthogonal projection of the second pad on the substrate does not overlap with an orthogonal projection of the second electronic component on the substrate.