# US 10,373,931 B2 · Semiconductor package structure and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,931 B2 - Document ID: US10373931B2 - Status: Granted - Kind: B2 - Application number: 15/441,901 - Filed: 2017-02-24 - Published: 2018-05-31 - Granted: 2019-08-06 - Earliest claimed: 2016-11-29 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: Jeng-Nan Hung; Chun-Hui Yu; Kuo-Chung Yee; Yi-Da Tsai; Wei-Hung Lin; Ming-Da Cheng; Ching-Hua Hsieh - Web page: https://patentgrep.com/patent/US10373931B2 ## CPC - H10W 90/00: Package configurations - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 74/01: Manufacture or treatment - H10W 74/016: {using moulds} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 72/01: {Manufacture or treatment} - H10W 72/073: {of die-attach connectors} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/354: {comprising polymers} - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 72/853: {On the same surface} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 74/014: {using batch processing} - H10W 74/017: {Auxiliary layers for moulds, e.g. release layers or layers preventing residue} - H10W 74/40: characterised by their materials - H10W 74/473: {containing a filler} - H10W 90/20: Configurations of stacked chips - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/732: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacturing a semiconductor package structure is provided. A stacked structure formed over the carrier substrate is provided, wherein the stacked structure has a channel with an opening. The stacked structure is immersed into a fluidic molding material to render the fluidic molding material flow into the channel through the openings. ## Claims ### Claim 1 A method of manufacturing a semiconductor package structure, comprising: providing a stacked structure formed over a carrier substrate, wherein the stacked structure comprises a plurality of first dies over the carrier substrate and spaced from each other, and a second die over the plurality of first dies, and the carrier substrate, the plurality of first dies and the second die defining a channel with an opening; and immersing the plurality of first dies and the second die of the stacked structure into a fluidic molding material to render the fluidic molding material flow into the channel through the opening, wherein the second die of the stacked structure is immersed into the fluidic molding material prior to the plurality of first dies are immersed into the fluidic molding material, wherein immersing the stacked structure into the fluidic molding material is performed in a reaction chamber, and the method further comprises vacuuming the reaction chamber during immersing the stacked structure into the fluidic molding material. ### Claim 2 (depends on 1) The method of claim 1, wherein the plurality of first dies are laterally disposed over the carrier substrate in a first direction, and the opening of the channel faces a second direction. ### Claim 3 (depends on 1) The method of claim 1, wherein the stacked structure is immersed into the fluidic molding material at a substantially constant rate. ### Claim 4 (depends on 1) The method of claim 1, further comprising heating the fluidic molding material when immersing the stacked structure into the fluidic molding material to maintain fluidity of the fluidic molding material. ### Claim 5 (depends on 1) The method of claim 1, further comprising suspending the stacked structure and the carrier substrate over a mold chase containing the fluidic molding material. ### Claim 6 (depends on 5) The method of claim 5, further comprising moving the stacked structure downward to immerse the channel into the fluidic molding material. ### Claim 7 (depends on 5) The method of claim 5, further comprising moving the mold chase upward to immerse the channel into the fluidic molding material. ### Claim 8 (depends on 1) The method of claim 1, further comprising curing the fluidic molding material to form a molding layer in the channel. ### Claim 9 (depends on 8) The method of claim 8, further comprising removing the carrier substrate from the stacked structure after the molding layer is formed. ### Claim 10 (depends on 1) The method of claim 1, wherein the fluidic molding material includes at least one filler, and a dimension of the opening of the channel is larger than a size of the filler of the fluidic molding material. ### Claim 11 A method of manufacturing a semiconductor package structure, comprising: providing a stacked structure having a channel with an opening; disposing the channel in a fluidic material at a first depth, wherein a first portion of the opening is immersed into the fluidic material at the first depth to render the fluidic material flow into the channel through the first portion of the opening, and residual air in the channel is exhausted from a second portion of the opening; and disposing the channel in the fluidic material at a second depth, wherein the second portion of the opening is further immersed into the fluidic material to render the fluidic material flow into the channel, wherein immersing the stacked structure into the fluidic molding material is performed in a reaction chamber, and the method further comprises vacuuming the reaction chamber during immersing the stacked structure into the fluidic molding material. ### Claim 12 (depends on 11) The method of claim 11, wherein disposing the channel in the fluidic material is performed in a heated environment to maintain fluidity of the fluidic material. ### Claim 13 (depends on 11) The method of claim 11, further comprising curing the fluidic material. ### Claim 14 (depends on 11) The method of claim 11, wherein the channel is immersed into the fluidic molding material in a continuous manner. ### Claim 15 (depends on 11) The method of claim 11, wherein the channel is immersed into the fluidic molding material in a multi-step manner. ### Claim 16 A method of manufacturing a semiconductor package structure, comprising: providing a stacked structure, wherein the stacked structure comprises a plurality of first dies spaced from each other, and a second die over the plurality of first dies, and the plurality of first dies and the second die define a channel with two or more openings; disposing the stacked structure in a reaction chamber; and immersing the plurality of first dies and the second die of the stacked structure into a fluidic molding material in the reaction chamber, wherein the method further comprises vacuuming the reaction chamber during immersing the stacked structure into the fluidic molding material to render the fluidic molding material flow into the channel through the openings, wherein the second die of the stacked structure is immersed into the fluidic molding material prior to the plurality of first dies are immersed into the fluidic molding material. ### Claim 17 (depends on 16) The method of claim 16, further comprising heating the fluidic molding material when immersing the stacked structure into the fluidic molding material to maintain fluidity of the fluidic molding material. ### Claim 18 (depends on 16) The method of claim 16, wherein the fluidic molding material includes at least one filler, and a dimension of the opening of the channel is larger than a size of the filler of the fluidic molding material.