# US 10,373,929 B2 · Method of manufacturing a semiconductor device

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- Number: US 10,373,929 B2
- Document ID: US10373929B2
- Status: Granted
- Kind: B2
- Application number: 15/905,570
- Filed: 2018-02-26
- Published: 2019-03-21
- Granted: 2019-08-06
- Earliest claimed: 2017-09-15
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Yoichiro Kurita
- Web page: https://patentgrep.com/patent/US10373929B2

## CPC

- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10P 14/60: of insulating materials
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/0198: {batch processes}
- H10W 72/50: Bond wires
- H10W 74/014: {using batch processing}
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07211: {Treating the bond pad before connecting, e.g. by applying flux or cleaning}
- H10W 72/073: {of die-attach connectors}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor device includes forming an insulation layer on a support body, selectively forming openings through the insulation layer, forming a conductor pattern in the openings, and above selected portions of, the insulation layer, mounting a first semiconductor element on the insulation layer and electrically connecting the first semiconductor element to the conductor pattern, forming a resin over the first semiconductor element and the insulation layer, removing the support body after the resin is formed to expose a surface of a portion of the conductor pattern, etching the exposed surface of the portion of the conductor pattern to form a recess over the portion of the conductor pattern, and forming a pad containing a metal different than the metal of the conductor pattern in the recess in contact with the conductor pattern.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming an insulation layer on a support body;
selectively forming openings through the insulation layer;
forming a conductor pattern in the openings, and above selected portions of, the insulation layer;
mounting a first semiconductor element on the insulation layer and electrically connecting the first semiconductor element to the conductor pattern;
forming a resin over the first semiconductor element and the insulation layer;
after the resin is formed, removing the support body to expose a surface of a portion of the conductor pattern;
etching the exposed surface of the portion of the conductor pattern to form a recess extending inwardly of a surface of the insulation layer over the portion of the conductor pattern; and
forming a pad containing a metal different than the metal of the conductor pattern in the recess in contact with the conductor pattern.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the portion of the conductor pattern that is recessed comprises copper.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the forming of the pad comprises forming a film containing at least one of gold and nickel.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the forming of the pad comprises:
forming a nickel film using electroless plating; and
forming a gold film using electroless plating.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the nickel film is deposited over the conductor pattern; and
the gold film is formed over the nickel film.

### Claim 6 (depends on 5)

The method according to claim 5, further comprising:
forming a palladium film on the nickel film before forming the gold film.

### Claim 7 (depends on 3)

The method according to claim 3, wherein the forming of the pad comprises:
forming a nickel film on the conductor pattern; and
replacing nickel of the nickel film with gold.

### Claim 8 (depends on 1)

The method according to claim 1, wherein a plurality of pads are provided and the pads are spaced from one another at a pitch of 40 μm or less.

### Claim 9 (depends on 1)

The method according to claim 1, further comprising:
bonding a second semiconductor element to the pad.

### Claim 10 (depends on 9)

The method according to claim 9, wherein
the first semiconductor element is a memory chip, and
the second semiconductor element is a controller chip for the memory chip.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the support body comprises at least one of a silicon substrate or a glass substrate.

### Claim 12 (depends on 1)

The method according to claim 1, wherein
the conductor pattern is formed on a seed layer previously formed on the support body by a plating method, and
the seed layer is removed to expose a surface of the portion of the conductor pattern after the support body is removed.