# US 10,373,924 B2 · Grid array connection device and method

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- Number: US 10,373,924 B2
- Document ID: US10373924B2
- Status: Granted
- Kind: B2
- Application number: 15/967,820
- Filed: 2018-05-01
- Published: 2018-08-30
- Granted: 2019-08-06
- Earliest claimed: 2005-06-27
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Munehiro Toyama; Siew Fong Tai; Kian Sin Sim; Charavanakumara Gurumurthy; Tamil Selvy Selvamuniandy
- Web page: https://patentgrep.com/patent/US10373924B2

## CPC

- H05K 3/244: {Finish plating of conductors, especially of copper conductors, e.g. for pads or lands (selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3465)}
- H10W 72/019: {of bond pads}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/245: {of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core}
- H10W 72/251: {Materials}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.

## Claims

### Claim 1

An electronic device comprising:
a chip package that includes a chip connection structure, to mount the chip package on a circuit board, wherein the chip connection structure includes:
a first layer that includes nickel (Ni); and
a second layer that includes palladium (Pd), disposed on the first layer, wherein the second layer comprises a substantially amorphous structure.

### Claim 2 (depends on 1)

The electronic device of claim 1, further comprising a metallic connection structure provided on a side of the chip package that is to be mounted on the circuit board, wherein the first layer is coupled with the metallic connection structure.

### Claim 3 (depends on 2)

The electronic device of claim 2, wherein the metallic connection structure comprises a pad.

### Claim 4 (depends on 1)

The electronic device of claim 1, wherein the second layer further comprises a substantially non-porous structure, to prevent corrosion of the first layer.

### Claim 5 (depends on 1)

The electronic device of claim 1, further comprising a third layer disposed on the second layer, wherein the third layer has a determined thickness.

### Claim 6 (depends on 5)

The electronic device of claim 5, wherein the third layer comprises gold, wherein the determined thickness of the third layer is between 50 and 80 μm.

### Claim 7 (depends on 2)

The electronic device of claim 2, wherein the metallic connection structure comprises copper (Cu).

### Claim 8 (depends on 1)

The electronic device of claim 1, wherein the second layer further includes phosphorus (P).

### Claim 9 (depends on 1)

The electronic device of claim 1, wherein the first layer further includes phosphorus (P).

### Claim 10 (depends on 1)

The electronic device of claim 1, wherein the chip connection structure provides an input/output connection between the chip package and the circuit board.

### Claim 11 (depends on 1)

The electronic device of claim 1, wherein the electronic device comprises a chip assembly, wherein the chip connection structure is to receive a pin provided on the circuit board.

### Claim 12 (depends on 1)

The electronic device of claim 1, wherein the first layer has a thickness between 5 and 8 μm.

### Claim 13 (depends on 1)

The electronic device of claim 1, wherein the second layer has a thickness of about 100 μm.

### Claim 14

A method comprising:
forming, on a chip package to be mounted on a circuit board, a first layer that includes nickel (Ni); and
forming a second layer that includes palladium (Pd), on the first layer, wherein forming the second layer includes providing a substantially amorphous structure for the second layer.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
providing a metallic connection structure on a side of the chip package that is to be mounted on the circuit board; and
coupling the first layer with the metallic connection structure.

### Claim 16 (depends on 14)

The method of claim 14, wherein forming the second layer further includes providing a substantially non-porous structure of the second layer, to prevent corrosion of the first layer.

### Claim 17 (depends on 14)

The method of claim 14, further comprising disposing a third layer disposed on the second layer, wherein the third layer has a determined thickness.

### Claim 18 (depends on 17)

The method of claim 17, wherein the third layer comprises gold, wherein the determined thickness of the third layer is between 50 and 80 μm.

### Claim 19 (depends on 14)

The method of claim 14, wherein the first layer further includes phosphorous (P).

### Claim 20 (depends on 14)

The method of claim 14, wherein the second layer further includes phosphorus (P).