# US 10,373,922 B2 · Methods of manufacturing a multi-device package

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- Number: US 10,373,922 B2
- Document ID: US10373922B2
- Status: Granted
- Kind: B2
- Application number: 14/731,382
- Filed: 2015-06-04
- Published: 2016-12-08
- Granted: 2019-08-06
- Earliest claimed: 2015-06-04
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Shih-Fan Kuan; Yi-Jen Lo
- Web page: https://patentgrep.com/patent/US10373922B2

## CPC

- H10W 72/90: Bond pads, in general
- H10D 84/01: Manufacture or treatment
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7422: {used to protect an active side of a device or wafer}
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01257: {by reflowing}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/853: {On the same surface}
- H10W 72/9413: {on encapsulations}
- H10W 74/014: {using batch processing}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

## Claims

### Claim 1

A method of manufacturing a multi-device package, the method comprising:
forming at least two device regions from a wafer and within the wafer by using material of the wafer;
forming a first redistribution layer on the wafer, the first redistribution layer being electrically connected to the at least two device regions to electrically integrate the at least two device regions;
forming a plurality of first connectors on the first redistribution layer;
mounting an external chip on the plurality of first connectors, the external chip being electrically connected to the first redistribution layer by the plurality of first connectors;
forming a plurality of second connectors on the first redistribution layer, a diameter of a second connector of the plurality of second connectors being larger than a sum of a diameter of a first connector of the plurality of first connectors and a thickness of the external chip;
forming a temporary adhesive layer covering the plurality of second connectors and the external chip;
thinning the wafer;
removing the temporary adhesive layer; and
thereafter dicing the wafer along a scribe line to form the multi-device package.

### Claim 2 (depends on 1)

The method of claim 1, wherein mounting the external chip comprises mounting the external chip having a first through hole.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming a molding layer covering the first redistribution layer and the external chip;
removing a portion of the molding layer to form a second through hole and a third through hole, the second through hole exposing the first redistribution layer, the third through hole being through the first through hole to expose the first redistribution layer; and
filling a conductive material in the first through hole, the second through hole, and the third through hole to form a first conductive contact and a second conductive contact.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
forming a second redistribution layer on the molding layer, the second redistribution layer being electrically connected to the first conductive contact and the second conductive contact; and
forming a plurality of third connectors on the second redistribution layer.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
forming a temporary adhesive layer covering the plurality of third connectors and the second redistribution layer;
thinning the wafer; and
removing the temporary adhesive layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the first redistribution layer on the wafer comprises:
depositing a dielectric material covering the wafer;
removing a portion of the dielectric material to form openings exposing the at least two device regions of the wafer;
forming vias in the openings;
forming a metal layer on the vias; and
patterning the metal layer.

### Claim 7 (depends on 4)

The method of claim 4, wherein forming the second redistribution layer on the molding layer comprises:
forming a dielectric material covering the molding layer;
removing a portion of the dielectric material to form openings exposing the first conductive contact and the second conductive contact;
forming vias in the openings;
forming a metal layer on the vias; and
patterning the metal layer.

### Claim 8

A method of manufacturing a multi-device package, the method comprising:
forming at least two device regions from a wafer and within the wafer by using material of the wafer;
forming a redistribution layer on the wafer, the redistribution layer being electrically connected to the at least two device regions to electrically integrate the at least two device regions;
forming a plurality of connectors on the redistribution layer;
mounting an external chip on the plurality of connectors, the external chip being electrically connected to the redistribution layer by the plurality of connectors;
performing testing of individual devices comprising the at least two device regions; and
thereafter dicing the wafer along a scribe line to form the multi-device package.

### Claim 9

A method of manufacturing a multi-device package, the method comprising:
forming at least two device regions from a wafer and within the wafer by using material of the wafer;
forming a redistribution layer on the wafer, the redistribution layer being electrically connected to the at least two device regions to electrically integrate the at least two device regions, wherein forming the redistribution layer on the wafer comprises forming conductive pads recessed within the wafer, wherein the conductive pads form an uppermost metal layer of a metal interconnect structure of the first redistribution layer;
forming a plurality of connectors on the redistribution layer;
mounting an external chip on the plurality of connectors, the external chip being electrically connected to the redistribution layer by the plurality of connectors; and
thereafter dicing the wafer along a scribe line to form the multi-device package.