# US 10,373,921 B2 · Power gate circuits for semiconductor devices

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- Number: US 10,373,921 B2
- Document ID: US10373921B2
- Status: Granted
- Kind: B2
- Application number: 15/628,343
- Filed: 2017-06-20
- Published: 2018-12-20
- Granted: 2019-08-06
- Earliest claimed: 2017-06-20
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Yasushi Matsubara
- Web page: https://patentgrep.com/patent/US10373921B2

## CPC

- H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)}
- G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}
- H02M 7/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10W 72/50: Bond wires
- H10W 90/00: Package configurations
- G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/408: Address circuits
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 72/07554: {changes in dispositions}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.

## Claims

### Claim 1

An apparatus, comprising:
a substrate;
a first wiring supplied with a power voltage, the first wiring being formed over the substrate and elongating in a first direction;
a second wiring formed between the substrate and the first wiring with vertically overlapping the first wiring, the second wiring elongating in the first direction;
a plurality of transistors vertically coupled between the first wiring and the second wiring;
a third wiring formed between the first wiring and the second wiring, the third wiring elongating in the first direction and being coupled to each of gates of the plurality of vertical transistors; and
an external terminal receiving a clock enable signal, wherein the third wiring is configured to receive a control signal of which logic level is controlled responsive to the clock enable signal.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the third wiring has a plurality of apertures each penetrated by a corresponding one of sets of gates and bodies of the plurality of transistors.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising a plurality of circuit blocks arranged in the first direction and under the second wiring, each of the plurality of circuit blocks being configured to be supplied with the power voltage from the second wiring.

### Claim 4

An apparatus, comprising:
a substrate;
a first wiring supplied with a power voltage, the first wiring being formed over the substrate and elongating in a first direction;
a second wiring formed between the substrate and the first wiring with vertically overlapping the first wiring, the second wiring elongating in the first direction:
a plurality of transistors vertically coupled between the first wiring and the second wiring;
a third wiring between the first wiring and the second wiring;
a fourth wiring between the third wiring and the second wiring; and
a plurality of additional transistors each coupled between a corresponding one of the plurality of transistors and the second wiring;
wherein the third wiring elongates in the first direction and coupled to each of gates of the plurality of transistors and
wherein the fourth wiring elongates in the first direction and coupled to each of gates of the plurality of additional transistors.

### Claim 5 (depends on 4)

The apparatus of claim 4, further comprising an external terminal receiving a clock enable signal, wherein the third wiring is configured to receive a control signal of which logic level is controlled responsive to the clock enable signal.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the fourth wiring is configured to receive the control signal.

### Claim 7 (depends on 5)

The apparatus of claim 5, further comprising a command decoder configured to output a row activate signal, wherein the fourth wiring is configured to receive an additional control signal of which logic level is controlled responsive to the row activate signal.

### Claim 8

An apparatus, comprising:
a plurality of circuit blocks, each circuit block including circuits;
a first conductive structure configured to be provided a supply voltage;
a second conductive structure configured to provide power to the circuits of the plurality of circuit blocks;
a third conductive structure configured to be provided a second supply voltage;
a fourth conductive structure configured to provide power to the circuits of the plurality of circuit blocks;
a plurality of vertical transistors disposed between the first and second conductive structures and configured to provide power from the first conductive structure to the second conductive structure when activated, each of the plurality of vertical transistors including a respective gate included in a gate electrode disposed between the first and second conductive structures; and
a second plurality of vertical transistors disposed between the third and fourth conductive structures and configured to provide power from the third conductive structure to the fourth conductive structure when activated, each of the second plurality of vertical transistors including a respective gate included in a second gate electrode disposed between the third and fourth conductive structures.

### Claim 9 (depends on 8)

The apparatus of claim 8 wherein each of the plurality of vertical transistors comprises a p-channel field effect transistor.

### Claim 10 (depends on 8)

The apparatus of claim 8 wherein each of the plurality of vertical transistors comprises an n-channel field effect transistor.

### Claim 11 (depends on 8)

The apparatus of claim 8 wherein each of the plurality of vertical transistors comprises a p-channel field effect transistor and wherein each of the second plurality of vertical transistors comprises an n-channel field effect transistor.

### Claim 12 (depends on 8)

The apparatus of claim 8 wherein the first conductive structure, the second conductive structure, and the gate electrode extend lengthwise adjacent the circuits of the plurality of circuit blocks.

### Claim 13

An apparatus, comprising:
a plurality of circuit blocks, each circuit block including circuits;
a first conductive structure configured to be provided a supply voltage;
a second conductive structure configured to provide power to the circuits of the plurality of circuit blocks; and
a plurality of pairs of vertical transistors disposed between the first and second conductive structures, each of the pairs of vertical transistors including stacked vertical transistors, the plurality of pairs of vertical transistors configured to provide power from the first conductive structure to the second conductive structure when activated, each of the plurality of pairs of vertical transistors including a first gate included in a first gate electrode disposed between the first and second conductive structures and further including a second gate included in a second gate electrode disposed between the first gate electrode and the second conductive structure.

### Claim 14 (depends on 13)

The apparatus of claim 13 wherein the first conductive structure, the second conductive structure, the first gate electrode, and the second gate electrode are arranged vertically and adjacent the circuits of the plurality of circuit blocks.

### Claim 15 (depends on 13)

The apparatus of claim 13 wherein the first and second gate electrodes are configured to receive a same signal to control activation of each of the plurality of pairs of vertical transistors.

### Claim 16 (depends on 13)

The apparatus of claim 13 wherein the stacked vertical transistors of each of the pairs of vertical transistors share a post of semiconductor material that extends between the first and second conductive structures.

### Claim 17 (depends on 13)

The apparatus of claim 13 wherein each the stacked vertical transistors of each of the pairs of vertical transistors includes a respective body having a circular cross-section.