# US 10,373,919 B2 · Semiconductor device and method of manufacturing semiconductor device

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- Number: US 10,373,919 B2
- Document ID: US10373919B2
- Status: Granted
- Kind: B2
- Application number: 15/666,534
- Filed: 2017-08-01
- Published: 2018-03-15
- Granted: 2019-08-06
- Earliest claimed: 2016-09-14
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Tatsuhiko Asai
- Web page: https://patentgrep.com/patent/US10373919B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- H10W 74/016: {using moulds}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 70/20: Conductive package substrates serving as an interconnection, e.g. metal plates (leadframes H10W70/40)
- H10W 72/07336: {Soldering or alloying}
- H10W 72/075: {of bond wires}
- H10W 72/076: {of strap connectors}
- H10W 72/07636: {Soldering or alloying}
- H10W 72/07653: {changes in shapes}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/634: {Cross-sectional shape}
- H10W 72/871: {Bond wires and strap connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/886: {Die-attach connectors and strap connectors}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 76/15: Containers comprising an insulating or insulated base
- H10W 76/47: Solid or gel fillings
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL}
- H10W 90/764: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device including a stacked assembly. The stacked assembly includes a metal substrate, a stacked substrate mounted on the metal substrate and having an electrode pattern, a semiconductor element mounted on the stacked substrate, and a lead frame interconnection electrically connecting the semiconductor element and the electrode pattern. The lead frame interconnection includes a first bonding portion in contact with the semiconductor element, a second bonding portion in contact with the electrode pattern, and an interconnect portion connecting the first and second bonding portions. At least one of the first bonding portion and the second bonding portion is wider than the interconnect portion.

## Claims

### Claim 1

A semiconductor device, comprising:
a stacked assembly including:
a metal substrate;
a stacked substrate mounted on the metal substrate, the stacked substrate having an electrode pattern;
a semiconductor element mounted on the stacked substrate; and
a monolithic lead frame interconnection electrically connecting the semiconductor element and the electrode pattern, the lead frame interconnection including
a first bonding portion that is a first plate, a bottom surface thereof being bonded to the semiconductor element by a first bonding member,
a second bonding portion that is a second plate, a bottom surface thereof being bonded to the electrode pattern by a second bonding member, and
an interconnect portion connecting the first and second bonding portions along a first direction, the interconnect portion being a bended rectangular plate, and having
a first end extending from a side surface of the first plate,
a second end extending from a side surface or a top surface of the second plate, and
an n-shaped central portion that extends from, and connects, the first and second ends, wherein
the first and second ends and the central portion of the interconnect portion are of a same width in a second direction perpendicular to the first direction, and
a width of at least one of the first bonding portion and the second bonding portion in the second direction, is larger than the width of the first or second end of the interconnect portion.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the interconnect portion is connected to one of the first and second bonding portions at a position away from an end of said one bonding portion.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
a threshold width of the interconnect portion is determinable by a targeted lifespan of the semiconductor device and at least one of a width of the first bonding portion and a width of the second bonding portion, and
a width of the interconnect portion is set to be narrower than the threshold width.

### Claim 4 (depends on 1)

The semiconductor device according claim 1, wherein said at least one bonding portion is at least 20% wider than the interconnect portion.

### Claim 5 (depends on 1)

The semiconductor device according claim 1, wherein the semiconductor device includes a resin case adhered to the stacked assembly.

### Claim 6

A method of manufacturing a semiconductor device, the method comprising:
assembling a stacked assembly by
mounting a semiconductor element on a stacked substrate and
mounting the stacked substrate on a metal substrate, the stacked substrate having an electrode pattern;
electrically connecting the semiconductor element and the electrode pattern using a monolithic lead frame interconnection having
a first bonding portion that is a first plate,
a second bonding portion that is a second plate, and
an interconnect portion connecting the first and the second bonding portions along a first direction, the interconnect portion being a bended rectangular plate, and having
a first end extending from a side surface of the first plate,
a second end extending from a side surface or a top surface of the second plate, and
an n-shaped central portion that extends from, and connects, the first and second ends, wherein
a bottom surface of the first plate and a bottom surface of the second plate are respectively bonded to the semiconductor element and the electrode pattern by a first bonding member and a second bonding member,
the first and second ends and the central portion of the interconnect portion are of a same width in a second direction perpendicular to the first direction, and
a width of at least one of the first and second bonding portions in the second direction is larger than the width of the first or second end of the interconnect portion; and
adhering a resin case to the stacked assembly.