# US 10,373,915 B1 · Method for monitoring semiconductor process

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- Number: US 10,373,915 B1
- Document ID: US10373915B1
- Status: Granted
- Kind: B1
- Application number: 16/202,104
- Filed: 2018-11-28
- Granted: 2019-08-06
- Earliest claimed: 2018-03-22
- Assignees: United Microelectronics Corp.; Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicants: United Microelectronics Corp.; Fujian Jinhua Integrated Circuit Co., Ltd.
- Inventors: Hsiao-Lin Hsu; En-Chiuan Liou; Yi-Ting Chen; Sho-Shen Lee
- Web page: https://patentgrep.com/patent/US10373915B1

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- G01B 11/272: {using photoelectric detection means}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- G01B 2210/56: Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 74/27: {Structural arrangements therefor}
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 46/503: {Located in scribe lines}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G01B: MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A measurement make includes four rectangular regions having a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally. A plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, are disposed within the first region. Each first inner pattern block comprises line patterns and a block pattern. The block pattern has multiple space patterns arranged therein. The first inner pattern block is rotational symmetrical to the first middle pattern block.

## Claims

### Claim 1

A method for monitoring a semiconductor process, comprising:
providing a wafer having thereon a material layer;
performing a semiconductor process comprising forming a measurement mark in the material layer, wherein the measurement mark comprises four rectangular regions arranged in a 2×2 array about a center, wherein the four rectangular regions comprise a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally, wherein a plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks is disposed in the first region, wherein each of the first inner pattern blocks comprises a plurality of line patterns extending along a first direction and a block pattern having a plurality of space patterns arranged therein, wherein each of the first middle pattern blocks comprises a plurality of line patterns extending along the first direction and a block pattern having a plurality of space patterns arranged therein, wherein the first inner pattern blocks are is rotationally symmetrical to the first middle pattern blocks;
measuring a first offset between the first inner pattern blocks and the first outer reference pattern blocks; and
measuring a second offset between the first middle pattern blocks and the first outer reference pattern blocks.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the measurement mark further comprises a plurality sets of second inner pattern blocks, second middle pattern blocks, and second outer reference pattern blocks disposed within the second region, wherein the plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks within the first region is rotationally symmetrical to the plurality sets of second inner pattern blocks, second middle pattern blocks, and second outer reference pattern blocks within the second region.

### Claim 3 (depends on 2)

The method according to claim 2 further comprising:
measuring a third offset between the second inner pattern blocks and the second outer reference pattern blocks; and
measuring a fourth offset between the second middle pattern blocks and the second outer reference pattern blocks.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the block pattern has a first longer side and a second longer side parallel to each other, wherein the first longer side is located between the plurality of space patterns and the plurality of line patterns.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the first inner pattern blocks, the first middle pattern blocks, and the first outer reference pattern blocks are disposed in a current layer on the wafer.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the first inner pattern blocks and the first middle pattern blocks are disposed in a current layer on the wafer, and the first outer reference pattern blocks are disposed in a pre-layer or a post-layer.