# US 10,373,914 B2 · Method of fabricating a three dimensional electronic structure

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- Number: US 10,373,914 B2
- Document ID: US10373914B2
- Status: Granted
- Kind: B2
- Application number: 15/620,375
- Filed: 2017-06-12
- Published: 2018-12-13
- Granted: 2019-08-06
- Earliest claimed: 2017-06-12
- Assignees: NewSouth Innovations Pty Limited
- Applicants: NewSouth Innovations Pty Limited
- Inventors: Joris Gerhard Keizer; Matthias Koch; Michelle Yvonne Simmons
- Web page: https://patentgrep.com/patent/US10373914B2

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- G06T 7/0008: {checking presence/absence}
- G06T 7/70: Determining position or orientation of objects or cameras (camera calibration G06T7/80)
- H10N 60/0912: {of Josephson-effect devices}
- H10N 60/12: Josephson-effect devices
- H10N 69/00: Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
- G06T 2207/30148: Semiconductor; IC; Wafer
- H10W 46/301: {for alignment}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

The present disclosure provides methods for fabricating multi-layered electronic architectures in silicon and/or germanium. In particular the disclosure provides an advanced marker design and a methodology for aligning devices on multiple layers of a multi-layered electronic architecture. The disclosure also provides a process for growing a semiconductor material with high quality surfaces.

## Claims

### Claim 1

An alignment marker for aligning electronic devices arranged on different planes of a multi-layered semiconductor architecture, the marker having a trenched structure comprising:
a central region arranged to host at least a portion of an electronic device, wherein the central region is located at a bottom of the trenched structure; and
a plurality of elongate regions radially extending from the central region, the plurality of elongate regions being arranged to host a plurality of conductive electrodes for control of the electronic device,
wherein the trenched structure is arranged in a manner such that, when a layer of semiconductor material is grown onto the marker, a further trenched structure is replicated on a surface of the grown layer of semiconductor material.

### Claim 2 (depends on 1)

The alignment marker of claim 1, wherein the replicated trenched structure has a shape that is substantially similar to the shape of the original trenched structure.

### Claim 3 (depends on 1)

The alignment marker of claim 1, wherein the trenched structure further comprises peripheral contact regions at end portions of the elongate regions, the contact regions being arranged to host contact pads.

### Claim 4 (depends on 1)

The alignment marker of claim 1, wherein the wall portion has a depth and a slope such that the marker is replicated with enough accuracy on a surface of the grown layer of semiconductor material when the thickness of the grown layer of semiconductor material is more than 100 nm.

### Claim 5 (depends on 1)

The alignment marker of claim 1, wherein the trenched structure that forms in the grown layer of semiconductor material is located above the marker, with an accuracy of about 20 nm.

### Claim 6 (depends on 1)

The alignment marker of claim 1, wherein the central region of the marker has a surface suitable to host an electronic device fabricated using the lithographic capabilities of an STM or SEM.

### Claim 7 (depends on 1)

The alignment marker of claim 1, wherein the trenched structure has a depth between about 100 nm and about 200 nm.

### Claim 8 (depends on 1)

The alignment marker of claim 1, wherein the width of the trenched structure at half depth is between about 50 nm and about 200 nm.

### Claim 9 (depends on 1)

The alignment marker of claim 1, wherein the trenched structure has a substantially flat region at the bottom of the trenches and the flat region has a width between about 100 nm and about 150 nm.

### Claim 10 (depends on 1)

The alignment marker of claim 1, wherein the semiconductor material is crystalline silicon, crystalline germanium or a silicon-germanium alloy.

### Claim 11

A method for aligning electronic elements on different planar surfaces of a multi-layered architecture with respect to each other, the method comprising the steps of:
providing a first planar surface of a semiconductor material comprising at least one marker in accordance with any one of the preceding claims and a first electronic element formed on the bottom of the trenched structure of the marker;
imaging the at least one marker with the electronic element;
determining the position of a reference point on the marker by using image data;
determining an offset between the reference point and the electronic element;
growing a further layer of the semiconductor material on the first planar surface in a manner such that the at least one marker is reproduced on a second planar surface; the second planar surface being a planar surface of the grown layer of the semiconductor material; and
forming a second electronic element in the reproduced marker whereby the position of the second electronic element in the reproduced marker is based on the position of the reference point and offset of the first electronic element.

### Claim 12 (depends on 11)

The method of claim 11, wherein the step of forming a second electronic element in the reproduced marker comprises the steps of:
imaging the reproduced marker;
determining the position of the reference point on the reproduced marker by using image data;
determining the position of the second electronic element based on the position of the reference point on the reproduced marker and the offset;
forming the second electronic element at the position of the second electronic element.

### Claim 13 (depends on 11)

The method of claim 11, wherein the position of a reference point on the marker, on the first planar surface or the grown surface, is determined by finding an intersection region of the central axis of each of the elongate trenched regions.

### Claim 14 (depends on 11)

The method of claim 11, wherein the second planar surface is the surface of an epitaxial silicon layer formed on the first planar surface.

### Claim 15 (depends on 11)

The method of claim 11, wherein the method comprises the step of forming a narrower neck portion in one of the elongate regions of the trenched structure and using the neck portion as a reference for positioning the electronic element.

### Claim 16 (depends on 11)

The method of claim 11, wherein the semiconductor material is crystalline silicon, crystalline germanium or a silicon-germanium alloy.

### Claim 17 (depends on 1)

A multi-layered electronic architecture comprising a plurality of electronic elements distributed on two or more planes of the architecture, the electronic elements being vertically aligned across planes with an accuracy below 20 nm using a marker in accordance with claim 1.

### Claim 18 (depends on 17)

The multi-layered electronic architecture of claim 17, wherein the architecture comprises a silicon layer.

### Claim 19 (depends on 17)

The multi-layered electronic architecture of claim 17, wherein the architecture comprises:
a plurality of qubit elements disposed in a two-dimensional matrix arrangement across the architecture; and
a plurality of control members, each control member being arranged to control a plurality of qubits of the architecture.