# US 10,373,912 B2 · Replacement metal gate processes for vertical transport field-effect transistor

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- Number: US 10,373,912 B2
- Document ID: US10373912B2
- Status: Granted
- Kind: B2
- Application number: 15/862,930
- Filed: 2018-01-05
- Published: 2019-07-11
- Granted: 2019-08-06
- Earliest claimed: 2018-01-05
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Choonghyun Lee; Chun Wing Yeung; Ruqiang Bao; Hemanth Jagannathan
- Web page: https://patentgrep.com/patent/US10373912B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0179: {the gate conductors having different shapes or dimensions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/0128: {Manufacturing their channels}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a semiconductor structure comprises forming a plurality of fins disposed over a top surface of a substrate and forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process. A gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin.

## Claims

### Claim 1

A method of forming a semiconductor structure, comprising:
forming a plurality of fins disposed over a top surface of a substrate; and
forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process;
wherein a gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin;
wherein forming the one or more VTFETs comprises:
forming bottom source/drain regions disposed over the top surface of the substrate surrounding the plurality of fins;
forming bottom spacers disposed over the bottom source/drain regions;
forming an oxide layer disposed over the bottom spacers and sidewalls of the plurality of fins;
forming a dummy gate disposed over the oxide layer;
recessing the dummy gate below top surfaces of the plurality of fins;
removing exposed portions of the oxide layer;
forming top spacers disposed over the dummy gate and the plurality of fins;
forming top junctions in upper portions of the plurality of fins;
forming an oxide layer disposed over the top spacers;
forming a liner disposed over the oxide layer; and
forming an interlevel dielectric layer disposed over the liner.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the one or more VTFETs comprises:
forming top source/drain openings in the interlevel dielectric layer to expose top surfaces of the top junctions of each of the plurality of fins;
forming top source/drain regions disposed over the top junctions;
forming top source/drain contact metal layers disposed over the top source/drain regions;
recessing the top source/drain contact metal layers below a top surface of the interlevel dielectric; and
forming top source/drain SAC capping layers disposed over the recessed top source/drain contact metal layers.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the one or more VTFETs further comprises:
forming a gate opening in the interlevel dielectric layer to expose a portion of the top spacer disposed over the dummy gate;
depositing a liner on sidewalls of the opening of the interlevel dielectric layer;
etching the exposed portion of the top spacer to expose a portion of the dummy gate;
removing the dummy gate;
performing the replacement metal gate process to form a gate dielectric surrounding the one or more fins and to form a metal gate conductor surrounding the gate dielectric;
filling the gate contact metal layer in remaining portions of the gate opening in the interlevel dielectric layer;
recessing the gate contact metal layer below the top surface of the interlevel dielectric layer; and
forming the gate SAC capping layer disposed over the recessed gate contact metal layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein forming the one or more VTFETs further comprises:
forming a bottom source/drain opening in the interlevel dielectric layer to expose a portion of the top surface of the bottom source/drain regions;
filling a bottom source/drain contact metal layer in the bottom source/drain opening disposed over the exposed portion of the top surface of the bottom source/drain regions;
recessing the bottom source/drain contact metal layer below a top surface of the interlevel dielectric layer; and
forming a bottom source/drain SAC capping layer disposed over the recessed bottom source/drain contact layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein forming the one or more VTFETs further comprises:
forming an additional liner disposed over the interlevel dielectric, the top source/drain SAC capping layers, the gate SAC capping layer and the bottom source/drain SAC capping layer;
forming an additional interlevel dielectric disposed over the additional liner;
forming vias in the additional liner, the additional interlevel dielectric, the top source/drain SAC capping layers, the gate SAC capping layer and the bottom source/drain SAC capping layer to expose portions of the top surfaces of the top source/drain contact metal layers, the gate contact metal layer and the bottom source/drain contact metal layer; and
forming top source/drain contacts, a gate contact and a bottom source/drain contact in the vias.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the one or more VTFETs further comprises forming at least one shallow trench isolation region in the substrate and the bottom source/drain region between a first subset of the plurality of fins and at least a second subset of the plurality of fins, wherein recessing the dummy gate comprises:
recessing a first portion of the dummy gate surrounding the first subset of the plurality of fins to a first depth; and
recessing a second portion of the dummy gate surrounding the second subset of the plurality of fins to a second depth greater than the first depth;
wherein the first subset of the plurality of fins form VTFETs having a first channel length; and
wherein the second subset of the plurality of fins form VTFETs having a second channel length smaller than the first channel length.

### Claim 7 (depends on 6)

The method of claim 6, wherein recessing the first portion of the dummy gate and recessing the second portion of the dummy gate comprises:
patterning a mask layer over the dummy gate to expose a top surface of the dummy gate disposed over the at least one shallow trench isolation region;
removing the exposed portion of the dummy gate to expose a portion of the bottom spacer disposed over the at least one shallow trench isolation region; and
forming an additional liner on exposed sidewalls of the dummy gate.

### Claim 8 (depends on 1)

The method of claim 1, wherein the dummy gate comprises a shared dummy gate surrounding pairs of the plurality of fins, each pair of the plurality of fins comprising:
a first fin forming a channel for one of a p-type field-effect transistor (PFET) of a given complementary metal-oxide-semiconductor (CMOS) device and an n-type field-effect transistor (NFET) of the given CMOS device; and
a second fin forming a channel for the other one of the PFET and the NFET of the given CMOS device.

### Claim 9

A method of forming a semiconductor structure, comprising:
forming a plurality of fins disposed over a top surface of a substrate; and
forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process;
wherein a gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin;
wherein forming the one or more VTFETs comprises:
forming bottom source/drain regions disposed over the top surface of the substrate surrounding the plurality of fins;
forming bottom spacers disposed over the bottom source/drain regions;
forming an oxide layer disposed over the bottom spacers and sidewalls of the plurality of fins;
forming a dummy gate disposed over the oxide layer;
recessing the dummy gate below top surfaces of the plurality of fins;
removing exposed portions of the oxide layer;
forming top spacers disposed over the dummy gate and the plurality of fins;
wherein the dummy gate comprises a shared dummy gate surrounding pairs of the plurality of fins, each pair of the plurality of fins comprising:
a first fin forming a channel for one of a p-type field-effect transistor (PFET) of a given complementary metal-oxide-semiconductor (CMOS) device and an n-type field-effect transistor (NFET) of the given CMOS device; and
a second fin forming a channel for the other one of the PFET and the NFET of the given CMOS device; and
wherein forming the one or more VTFETs further comprises:
patterning a gate opening in an interlevel dielectric layer disposed over a top spacer disposed over the shared dummy gate;
removing portions of the interlevel dielectric layer to expose a portion of the top surface of the top spacer;
forming a liner on exposed sidewalls of the interlevel dielectric layer in the gate opening; and
removing the shared dummy gate.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the one or more VTFETs further comprises:
forming a gate dielectric surrounding the first fin and the second fin;
forming a first gate conductor layer surrounding the gate dielectric, the top surface of the substrate, and the liner disposed on the exposed sidewalls of the interlevel dielectric layer;
blocking a first portion of the gate opening and the first gate conductor layer surrounding the first fin with an organic polymer layer;
removing the first gate conductor layer surrounding the second fin exposed by the organic polymer layer;
removing the organic polymer layer; and
forming a second gate conductor layer surrounding the gate dielectric surrounding second fin.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
filling the gate contact metal layer in the gate opening contacting the first gate conductor layer and the second gate conductor layer;
recessing the gate contact metal layer below a top surface of the interlevel dielectric; and
forming the gate SAC capping layer disposed over the recessed gate contact metal layer.

### Claim 12

A semiconductor structure, comprising:
a substrate; and
a plurality of fins disposed over a top surface of the substrate, the plurality of fins comprising channels for one or more vertical transport field-effect transistors (VTFETs) formed with a replacement metal gate (RMG) process;
wherein a given one of the VTFETs comprises a gate surrounding at least one of the plurality of fins, the gate of the given VTFET comprising a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin;
a bottom source/drain region disposed over the top surface of the substrate surrounding the plurality of fins;
a bottom spacer disposed over the bottom source/drain region;
the gate surrounding the plurality of fins;
a top spacer disposed over the gate;
top source/drain regions disposed over a portion of the top spacer disposed over each of the plurality of fins;
top source/drain contact metal layers disposed over the top source/drain regions;
top source/drain SAC capping layers disposed over the top source/drain metal contact layers;
a bottom source/drain contact metal layer disposed over a portion of the bottom source/drain region; and
a bottom source/drain SAC capping layer disposed over the bottom source/drain metal contact layer;
wherein the gate of the given VTFET comprises a shared gate surrounding pairs of the plurality of fins, each pair of the plurality of fins comprising:
a first fin forming a channel for one of a p-type field-effect transistor (PFET) of a given complementary metal-oxide-semiconductor (CMOS) device and an n-type field-effect transistor (NFET) of the given CMOS device; and
a second fin forming a channel for the other one of the PFET and the NFET of the given CMOS device.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein at least two of the plurality fins have different heights.

### Claim 14 (depends on 12)

The semiconductor structure of claim 12, wherein the shared gate comprises a first gate conductor surrounding the first fin and a second gate conductor surrounding the second fin, the gate contact metal layer contacting the first gate conductor and the second gate conductor.

### Claim 15

An integrated circuit comprising:
one or more vertical transport field-effect transistors (VTFETs) comprising:
a substrate; and
a plurality of fins disposed over a top surface of the substrate, the plurality of fins comprising channels for the one or more VTFETs formed with a replacement metal gate (RMG) process;
wherein a given one of the VTFETs comprises a gate surrounding at least one of the plurality of fins, the gate of the given VTFET comprising a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin;
wherein the one or more VTFETs further comprise:
a bottom source/drain region disposed over the top surface of the substrate surrounding the plurality of fins;
a bottom spacer disposed over the bottom source/drain region;
the gate surrounding the plurality of fins;
a top spacer disposed over the gate;
top source/drain regions disposed over a portion of the top spacer disposed over each of the plurality of fins;
top source/drain contact metal layers disposed over the top source/drain regions;
top source/drain SAC capping layers disposed over the top source/drain metal contact layers;
a bottom source/drain contact metal layer disposed over a portion of the bottom source/drain region; and
a bottom source/drain SAC capping layer disposed over the bottom source/drain metal contact layer;
wherein the gate of the given VTFET comprises a shared gate surrounding pairs of the plurality of fins, each pair of the plurality of fins comprising:
a first fin forming a channel for one of a p-type field-effect transistor (PFET) of a given complementary metal-oxide-semiconductor (CMOS) device and an n-type field-effect transistor (NFET) of the given CMOS device; and
a second fin forming a channel for the other one of the PFET and the NFET of the given CMOS device.

### Claim 16 (depends on 15)

The integrated circuit of claim 15, wherein at least two of the plurality fins have different heights.

### Claim 17 (depends on 15)

The integrated circuit of claim 15, wherein the shared gate comprises a first gate conductor surrounding the first fin and a second gate conductor surrounding the second fin, the gate contact metal layer contacting the first gate conductor and the second gate conductor.