# US 10,373,911 B2 · Semiconductor device and fabrication method thereof

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- Number: US 10,373,911 B2
- Document ID: US10373911B2
- Status: Granted
- Kind: B2
- Application number: 15/945,883
- Filed: 2018-04-05
- Published: 2018-10-11
- Granted: 2019-08-06
- Earliest claimed: 2017-04-07
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufactring International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Hai Yang Zhang; Cheng Long Zhang; Xin Jiang
- Web page: https://patentgrep.com/patent/US10373911B2

## CPC

- H10W 20/4462: {Carbon or carbon-containing materials, e.g. graphene}
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P 50/266: {by vapour etching only}
- H10P 50/283: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/045: {for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/087: {involving multiple stacked pre-patterned masks}
- H10W 20/088: {involving partial etching of via holes}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10P 52/403: {of conductive or resistive materials}
- H10W 20/0425: {comprising multiple stacked seed or nucleation layers}
- H10W 20/0554: {of nanotubes or nanowires}
- H10W 20/42: Vias, e.g. via plugs
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor device and fabrication method are provided. The method includes: providing a base substrate with a bottom metallic layer in the base substrate and a dielectric layer on the base substrate; forming interconnect openings through the dielectric layer and exposing the bottom metallic layer, where each interconnect openings includes a contacting hole and a groove on the contacting hole; forming a first conducting layer in the contacting hole, where the first conducting layer is made of a material having a first conductivity along a direction from the bottom metallic layer to a top surface of the first conducting layer; and after forming the first conducting layer, forming a second conducting layer in the groove, where the second conducting layer is made of a material having a second conductivity along a direction parallel to the top surface of the base substrate and the first conductivity is greater than the second conductivity.

## Claims

### Claim 1

A fabrication method of a semiconductor device, comprising:
providing a base substrate with a bottom metallic layer in the base substrate;
providing a dielectric layer on the base substrate;
forming interconnect openings, through the dielectric layer, and exposing the bottom metallic layer, each interconnect opening including a contacting hole and a groove on the contacting hole;
forming a barrier seed structure on the inner sidewalls of the groove, on the inner sidewalls of the contacting hole, and on the dielectric layer, and forming a catalytic matrix layer on top of the barrier seed structure;
forming a first conducting layer in the contacting hole, wherein the first conducting layer is made of a material having a first conductivity along a direction from the bottom metallic layer to a top surface of the first conducting layer;
after forming the first conducting layer, forming a second conducting layer in the groove, wherein the second conducting layer is made of a material having a second conductivity along a direction parallel to a top surface of the base substrate, and the first conductivity is greater than the second conductivity, wherein the first conducting layer and the second conducting layer are isolated from the dielectric layer by the barrier seed structure and the catalytic matrix layer.

### Claim 2 (depends on 1)

The fabrication method according to claim 1, wherein:
the first conducting layer is made of carbon nanotubes; and
the carbon nanotubes have an extending direction parallel to the direction from the bottom metallic layer to the top surface of the first conducting layer.

### Claim 3

A fabrication method of a semiconductor device, comprising:
providing a base substrate with a bottom metallic layer in the base substrate;
providing a dielectric layer on the base substrate;
forming interconnect openings, through the dielectric layer, and exposing the bottom metallic layer, each interconnect opening including a contacting hole and a groove on the contacting hole;
forming a first conducting layer in the contacting hole, wherein the first conducting layer is made of a material having a first conductivity along a direction from the bottom metallic layer to a top surface of the first conducting layer,
wherein forming the first conducting layer includes:
forming a first conducting material layer in the groove, in the contacting hole and on the dielectric layer;
removing a first portion of the first conducting material layer on the dielectric layer; and
removing a second portion of the first conducting material layer from the groove to form the first conducting layers;
after forming the first conducting layer, forming a second conducting layer in the groove, wherein the second conducting layer is made of a material having a second conductivity along a direction parallel to a top surface of the base substrate, and the first conductivity is greater than the second conductivity.

### Claim 4 (depends on 3)

The fabrication method according to claim 3, wherein:
the first conducting layer is formed by a catalytic chemical vapour deposition method, the method further including:
before performing the catalytic chemical vapour deposition method, forming a catalyst layer on inner sidewalls of the groove, on inner sidewalls of the contacting hole, and on the dielectric layer, wherein the first conducting layer is then formed on a surface of the catalyst layer; and
when removing the first portion of the conducting material layer from the dielectric layer, removing a portion of the catalyst layer from the dielectric layer.

### Claim 5 (depends on 4)

The fabrication method according to claim 4, wherein
the catalyst layer is made of cobalt nanoparticles, iron nanoparticles, nickel nanoparticles or a combination thereof.

### Claim 6 (depends on 4)

The fabrication method according to claim 4, further including:
before forming the catalyst layer, forming a catalytic matrix layer on the inner sidewalls of the groove, on the inner sidewalls of the contacting hole, and on the dielectric layer, followed by forming the catalyst layer on a surface of the catalytic matrix layer; and
when removing the first portion of the conducting material layer from the dielectric layer, removing a portion of the catalytic matrix layer and the portion of the catalyst layer from the dielectric layer.

### Claim 7 (depends on 6)

The fabrication method according to claim 6, wherein the catalytic matrix layer is made of a material including copper.

### Claim 8 (depends on 6)

The fabrication method according to claim 6, wherein forming the catalytic matrix layer includes:
forming an initial catalytic matrix layer on the inner sidewalls of the groove, on the inner sidewalls of the contacting hole, and on the dielectric layer; and
annealing the initial catalytic matrix layer to form the catalytic matrix layer.

### Claim 9 (depends on 8)

The fabrication method according to claim 8, wherein the initial catalytic matrix layer is made of Cu3N when the matrix layer is made of copper.

### Claim 10 (depends on 8)

The fabrication method according to claim 8, wherein the initial catalytic matrix layer is formed by an atomic layer deposition process.

### Claim 11 (depends on 6)

The fabrication method according to claim 6, further including:
before forming the catalytic matrix layer, forming a barrier seed structure on the inner sidewalls of the groove, on the inner sidewalls of the contacting hole, and on the dielectric layer, followed by forming the catalytic matrix layer on the barrier seed structure; and
when removing the first portion of the conducting material layer from the dielectric layer, removing the portion of the catalytic matrix layer, the portion of the catalyst layer and a portion of the barrier seed structure on the dielectric layer.

### Claim 12 (depends on 11)

The fabrication method according to claim 11, wherein the barrier seed structure include:
a first barrier seed layer on the inner sidewalls of the groove and contacting hole; and
a second barrier seed layer on a surface of the first barrier seed layer, wherein the second barrier seed layer is between the first barrier seed layer and the catalytic matrix layer.

### Claim 13 (depends on 12)

The fabrication method according to claim 12, wherein:
the first barrier seed layer is made of tantalum and the second barrier seed layer is made of TaN, or
the first barrier seed layer is made of titanium and the second barrier seed layer is made of TiN.

### Claim 14 (depends on 3)

The fabrication method according to claim 3, wherein
the first portion of the first conducting material layer is removed from the dielectric layer by a planarizing process; and
the second portion of the first conducting material layer is removed from the groove by an etching process.

### Claim 15 (depends on 14)

The fabrication method according to claim 14, wherein the etching process is a dry etching process using a gas including O2, CO2, CO, SO2 or a combination thereof.

### Claim 16 (depends on 1)

The fabrication method according to claim 1, wherein the second conducting layer is made of one or more metals.

### Claim 17

A semiconductor device, comprising:
a base substrate containing a bottom metallic layer therein;
a dielectric layer on the base substrate, wherein interconnect openings are through the dielectric layer to expose the bottom metallic layer, each interconnect opening including a contacting hole and a groove on the contacting hole;
a barrier seed structure on the inner sidewalls of the groove, on the inner sidewalls of the contacting hole, and on the dielectric layer;
a catalytic matrix layer on top of the barrier seed structure;
a first conducting layer in the contacting hole, wherein the first conducting layer is made of a material having a first conductivity along a direction from the bottom metallic layer to a top surface of the first conducting layer; and
a second conducting layer in the groove, wherein the second conducting layer is made of a material having a second conductivity along a direction parallel to a top surface of the base substrate, and the first conductivity is greater than the second conductivity, wherein the first conducting layer and the second conducting layer are isolated from the dielectric layer by the barrier seed structure and the catalytic matrix layer.

### Claim 18 (depends on 17)

The semiconductor device according to claim 17, wherein the first conducting layer is made of carbon nanotubes and the carbon nanotubes have an extending direction parallel to the direction from the bottom metallic layer to the top surface of the first conducting layer.

### Claim 19 (depends on 17)

The semiconductor device according to claim 17, further including the barrier seed structure between the first conducting layer and the dielectric layer, and between the second conducting layer and the dielectric layer.

### Claim 20 (depends on 19)

The semiconductor device according to claim 19, wherein the barrier seed structure includes:
a first barrier seed layer on the inner sidewalls of the groove and contacting hole; and
a second barrier seed layer on the first barrier seed layer, between the first barrier seed layer and the first conducting layer, and between the first barrier seed layer and the second conducting layer.