# US 10,373,910 B2 · Metal alloy capping layers for metallic interconnect structures

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- Number: US 10,373,910 B2
- Document ID: US10373910B2
- Status: Granted
- Kind: B2
- Application number: 15/807,793
- Filed: 2017-11-09
- Published: 2018-03-15
- Granted: 2019-08-06
- Earliest claimed: 2016-08-25
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Chih-Chao Yang
- Web page: https://patentgrep.com/patent/US10373910B2

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)}
- H10W 20/049: {by diffusing alloying elements}
- H10W 20/0523: {by irradiating with ultraviolet or particle radiation}
- H10W 20/0526: {by thermal treatment thereof}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/095: {by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096)}
- H10W 20/096: {by contacting with gases, liquids or plasmas}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/4424: {Copper alloys}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device is provided which comprises a metal interconnect structure having a metal alloy capping layer formed within a surface region of the metal interconnect structure, as well as methods for fabricating the semiconductor device. For example, a method comprises forming a metal interconnect structure in a dielectric layer, and applying a surface treatment to a surface of the metal interconnect structure to form a point defect layer in the surface of the metal interconnect structure. A metallic capping layer is then formed on the point defect layer of the metal interconnect structure, and a thermal anneal process is performed to convert the point defect layer into a metal alloy capping layer by infusion of metal atoms of the metallic capping layer into the point defect layer. The resulting metal alloy capping layer comprises an alloy of metallic materials of the metal capping layer and the metal interconnect structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a metal interconnect structure disposed in a dielectric layer, wherein the metal interconnect structure comprises a first metallic material, and wherein the dielectric layer comprises an upper densified surface layer;
a metallic capping layer disposed on a surface of the metal interconnect structure, wherein the metallic capping layer comprises a second metallic material; and
a metal alloy capping layer integrally disposed within an upper surface region of the metal interconnect structure, wherein an upper surface of metal alloy capping layer is coplanar with the upper densified surface layer of the dielectric layer;
wherein the metal alloy capping layer comprises an alloy of the first metallic material of the metal interconnect structure and the second metallic material of the metallic capping layer; and
wherein the metal alloy capping layer comprises metallic atoms of the second metallic material of the metallic capping layer infused into vacancy point defects within a layer of vacancy point defects formed in the upper surface region of the metal interconnect structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first metallic material comprises copper.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the second metallic material comprises at least one Co, Mn, Al, Ru, Ti, and Ni.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the metal interconnect structure and the dielectric layer comprise an interconnect level of a BEOL (back end of line) structure of the semiconductor device.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the metal alloy capping layer comprises a thickness in a range of about 1 nm to about 3 nm.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the metal alloy capping layer comprises a substantially uniform concentration proportion of the first metallic material and the second metallic material.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the metal alloy capping layer comprises a graded concentration proportion of the first metallic material and the second metallic material.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the layer of vacancy point defects in the upper surface region of the metal interconnect structure has a thickness in a range of about 1 nm to about 3 nm.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the layer of vacancy point defects in the upper surface region of the metal interconnect structure comprises a substantially uniform concentration of vacancy point detects in the upper surface region of the metal interconnect structure.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the layer of vacancy point defects in the upper surface region of the metal interconnect structure comprises a graded concentration of vacancy point defects in the upper surface region of the metal interconnect structure.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the upper densified surface layer of the dielectric layer has thickness in a range of about 1 nm to about 3 nm.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the upper densified surface layer of the dielectric layer comprises atoms infused into the upper surface of the dielectric layer.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the infused atoms comprise at least one of Si, C, N, H, and O atoms.

### Claim 14

A semiconductor device, comprising:
a metal interconnect structure disposed in a dielectric layer, wherein the metal interconnect structure comprises a first metallic material, and wherein the dielectric layer comprises an upper densified surface layer;
a metallic capping layer disposed on a surface of the metal interconnect structure, wherein the metallic capping layer comprises a second metallic material; and
a metal alloy capping layer integrally disposed within an upper surface region of the metal interconnect structure, wherein an upper surface of metal alloy capping layer is coplanar with the upper densified surface layer of the dielectric layer;
wherein the metal alloy capping layer comprises an alloy of the first metallic material and the second metallic material;
wherein the metal alloy capping layer comprises metallic atoms of the second metallic material of the metallic capping layer infused into vacancy point defects within a layer of vacancy point defects formed in the upper surface region of the metal interconnect structure;
wherein the metal alloy capping layer comprise a first sublayer and a second sublayer;
wherein the first sublayer comprises a first concentration of atoms of the second metallic material of the metallic capping layer infused into the vacancy point defects in the upper surface region of the metal interconnect structure;
wherein the second sublayer comprises a second concentration of atoms of the second metallic material of the metallic capping layer infused into the vacancy point defects in the upper surface region of the metal interconnect structure; and
wherein the first concentration of atoms of the second metallic material is greater than the second concentration of atoms of the second metallic material.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the first metallic material comprises copper.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the second metallic material comprises at least one Co, Mn, Al, Ru, Ti, and Ni.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein the metal interconnect structure and the dielectric layer comprise an interconnect level of a BEOL (back end of line) structure of the semiconductor device.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein the upper densified surface layer of the dielectric layer has thickness in a range of about 1 nm to about 3 nm.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the upper densified surface layer of the dielectric layer comprises atoms infused into the upper surface of the dielectric layer, wherein the infused atoms comprise at least one of Si, C, N, H, and O atoms.