# US 10,373,909 B2 · Selective surface modification of interconnect structures

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- Number: US 10,373,909 B2
- Document ID: US10373909B2
- Status: Granted
- Kind: B2
- Application number: 15/724,367
- Filed: 2017-10-04
- Published: 2018-03-22
- Granted: 2019-08-06
- Earliest claimed: 2016-09-19
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Raghuveer R. Patlolla; Cornelius Brown Peethala; Roger A. Quon; Chih-Chao Yang
- Web page: https://patentgrep.com/patent/US10373909B2

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor structures including copper interconnect structures and methods include selective surface modification of copper by providing a CuxTiyNz alloy in the surface. The methods generally include forming a titanium nitride layer on an exposed copper surface followed by annealing to form the CuxTiyNz, alloy in the exposed copper surface. Subsequently, the titanium layer is removed by a selective wet etching.

## Claims

### Claim 1

A semiconductor structure comprising:
at least one copper interconnect structure filled with copper in an interlayer dielectric, the at least one copper interconnect structure comprising a CuxTiyNz alloy in a top surface of the copper, wherein 0<x<1, 0<y<1, and 0≤z<1, wherein the CuxTiyNz alloy in the top surface is free of TiN thereon.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the at least one copper interconnect structure further comprises a liner layer on surfaces between the at least one copper interconnect structure and the interlayer dielectric.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1 further comprising a liner layer intermediate the copper and the interlayer dielectric formed of a material comprising tantalum, titanium, tantalum nitride or titanium nitride.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the top surface of the copper is coplanar to a top surface of the interlay dielectric.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the copper includes an alloying element comprising C, N, O, or Cl.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the copper further comprises an amount of an alloying element is in the range of about 0.001 weight percent (wt. %) to about 10 wt % of the copper.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the interlayer dielectric comprises silicon dioxide, silicon nitride, or a doped glass layer, such as phosphorus silicate glass, or boron silicate glass.

### Claim 8 (depends on 3)

The semiconductor structure of claim 3, wherein the liner layer comprises tantalum, tantalum, nitride, cobalt, ruthenium, titanium nitride, or combinations thereof.

### Claim 9 (depends on 2)

The semiconductor structure of claim 2, further comprising a seed layer on the liner layer, the seed layer comprising one or more metals.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the seed layer comprising the one or more metals is from 1 atomic percent to 10 atomic percent.

### Claim 11 (depends on 9)

The semiconductor structure of claim 9, wherein the seed layer comprises copper or copper manganese.

### Claim 12 (depends on 9)

The semiconductor structure of claim 9, wherein the seed layer comprising the one or more metals is from 1 atomic percent to 7 atomic percent.

### Claim 13 (depends on 5)

The semiconductor structure of claim 5, wherein the alloying element is from 0.001 weight percent to 10 weight percent.