# US 10,373,908 B2 · Dielectric thermal conductor for passivating eFuse and metal resistor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,908 B2 - Document ID: US10373908B2 - Status: Granted - Kind: B2 - Application number: 15/850,564 - Filed: 2017-12-21 - Published: 2018-05-17 - Granted: 2019-08-06 - Earliest claimed: 2015-09-02 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Qing Cao; Kangguo Cheng; Zhengwen Li; Fei Liu - Web page: https://patentgrep.com/patent/US10373908B2 ## CPC - H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 84/0135: {Manufacturing their gate conductors} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10P 14/414: {of metal-silicide materials} - H10P 14/6902: {composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon} - H10W 20/43: Layouts of interconnections - H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)} - H10W 20/48: Insulating materials thereof - H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive} - H10W 20/498: {Resistive arrangements or effects of, or between, wiring layers} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 40/254: {Diamond} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a first dielectric layer formed on a second dielectric layer and planar contacts formed in the second dielectric layer. The planar contacts are spaced apart to form a gap therebetween. The first dielectric layer includes a thermally conductive dielectric layer and is formed on lateral sides of the planar contacts and in the gap. A resistive element is formed between the planar contacts over the gap and in contact with at least the thermally conductive dielectric layer in the gap. ## Claims ### Claim 1 A method for forming a semiconductor device, comprising: forming at least one heat sink in a first dielectric layer, the at least one heat sink configured to dissipate heat; patterning a thermally conductive dielectric layer to form planar contacts within the thermally conductive dielectric layer and in contact or in near contact with the at least one heat sink; and forming a resistive element between the planar contacts over a gap and in contact with at least the thermally conductive dielectric layer in the gap. ### Claim 2 (depends on 1) The method as recited in claim 1, wherein the at least one heat sink includes two heat sinks formed on opposite sides of the resistive element and being disposed outside a footprint of the resistive element. ### Claim 3 (depends on 1) The method as recited in claim 1, wherein forming the resistive element includes forming a fuse from a metal silicide. ### Claim 4 (depends on 1) The method as recited in claim 1, wherein the thermally conductive dielectric layer includes diamond-like carbon. ### Claim 5 (depends on 1) The method as recited in claim 1, wherein the thermally conductive dielectric layer includes a circular shape. ### Claim 6 (depends on 1) The method as recited in claim 1, wherein the at least one heat sink is formed in a gate structure. ### Claim 7 (depends on 1) The method as recited in claim 1, wherein forming the resistive element includes forming the resistive element to extend over the planar contacts to contact the thermally conductive dielectric layer at end portions of the resistive element to increase heat dissipation. ### Claim 8 (depends on 1) The method as recited in claim 1, wherein the patterning the thermally conductive dielectric layer includes: depositing a conductive material in the thermally conductive dielectric material; and planarizing the conductive material. ### Claim 9 (depends on 1) The method as recited in claim 1, wherein the resistive element extends over the planar contacts and is in contact with the thermally conductive dielectric layer at end portions of the resistive element. ### Claim 10 (depends on 1) The method as recited in claim 1, further comprising forming a second dielectric on the at least one heat sink, the second dielectric layer separating the at least one heat sink from the planar contacts. ### Claim 11 A method for forming a semiconductor device, comprising: forming at least one heat sink on a substrate, the at least one heat sink configured to dissipate heat; forming a thermally conductive dielectric layer over the at least one heat sink; forming planar contacts in the thermally conductive dielectric layer and each planar contact in contact or in near contact with a corresponding one of the at least one heat sink; and forming a resistive element between the planar contacts over the gap and in contact with at least the thermally conductive dielectric layer in the gap. ### Claim 12 (depends on 11) The method as recited in claim 11, wherein the at least one heat sink includes two heat sinks formed on opposite sides of the resistive element and being disposed outside a footprint of the resistive element. ### Claim 13 (depends on 11) The method as recited in claim 11, wherein forming the resistive element includes forming a fuse from a metal silicide. ### Claim 14 (depends on 11) The method as recited in claim 11, wherein the thermally conductive dielectric layer includes diamond-like carbon. ### Claim 15 (depends on 11) The method as recited in claim 11, wherein the thermally conductive dielectric layer includes a circular shape. ### Claim 16 (depends on 11) The method as recited in claim 11, wherein the at least one heat sink is formed in a gate structure. ### Claim 17 (depends on 11) The method as recited in claim 11, wherein forming the resistive element includes forming the resistive element to extend over the planar contacts to contact the thermally conductive dielectric layer at end portions of the resistive element to increase heat dissipation. ### Claim 18 (depends on 11) The method as recited in claim 11, wherein the substrate is selected from the group consisting from a semiconductor-on-insulator substrate and a bulk semiconductor substrate. ### Claim 19 (depends on 11) The method as recited in claim 11, wherein forming the planar contact includes: patterning the thermally conductive dielectric layer; depositing a conductive material in the thermally conductive dielectric material; and planarizing the conductive material. ### Claim 20 (depends on 11) The method as recited in claim 11, wherein the resistive element extends over the planar contacts and is in contact with the thermally conductive dielectric layer at end portions of the resistive element.