# US 10,373,902 B2 · Fully molded miniaturized semiconductor module

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- Number: US 10,373,902 B2
- Document ID: US10373902B2
- Status: Granted
- Kind: B2
- Application number: 15/825,055
- Filed: 2017-11-28
- Published: 2018-04-19
- Granted: 2019-08-06
- Earliest claimed: 2011-12-30
- Assignees: DECA Technologies Inc.
- Applicants: DECA Technologies Inc.
- Inventors: Christopher M. Scanlan; Timothy L. Olson
- Web page: https://patentgrep.com/patent/US10373902B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/098: {Applying pastes or inks, e.g. screen printing (H10W70/095 takes precedence)}
- H10W 70/685: comprising multiple insulating layers
- H10W 70/69: Insulating materials thereof
- H10W 72/00: Interconnections or connectors in packages
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 70/656: Fan-in layouts
- H10W 70/66: Conductive materials thereof
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01257: {by reflowing}
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/0198: {batch processes}
- H10W 72/071: {Connecting or disconnecting}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07237: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/225: {Bumps having a filler embedded in a matrix}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/354: {comprising polymers}
- H10W 72/874: {On different surfaces}
- H10W 72/90: Bond pads, in general
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/144: {the encapsulations comprising foils}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imagable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

## Claims

### Claim 1

A semiconductor module, comprising:
a fully molded base portion comprising:
a planar surface,
a semiconductor die disposed within the fully molded base portion, the semiconductor die comprising an active surface comprising contact pads,
conductive pillars coupled to the contact pads and the conductive pillars extending to the planar surface, and
an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion;
a build-up interconnect structure comprising a conductive via, the build-up interconnect structure being contained within a footprint of the fully molded base portion, a position or alignment of the conductive via being adjusted by unit specific patterning to account for shift of the semiconductor die;
surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars; and
a SMD component electrically coupled to the SMD land pads with surface mount technology (SMT).

### Claim 2 (depends on 1)

The semiconductor module of claim 1, wherein the SMD component comprises at least one of a semiconductor die, a wafer level chip scale package (WLCSP), an integrated circuit (IC), a surface mount device, an active device, or a passive device or a solderable passive such as a resistor or a capacitor.

### Claim 3 (depends on 1)

The semiconductor module of claim 1, wherein the SMD component being electrically coupled to the SMD land pads further comprises:
the SMD component comprising solderable terminations;
solder paste disposed over the SMD land pads; and
the solderable terminations being disposed over, and electrically coupled to, the SMD land pads while the solderable terminations are in contact with the solder paste.

### Claim 4 (depends on 3)

The semiconductor module of claim 3, wherein SMD land pads comprise a solderable surface finish of: nickel (Ni) and gold (Au); Ni, palladium (Pd) and Au; tin (Sn); solder; or Organic Solderability Preservative (OSP).

### Claim 5 (depends on 1)

The semiconductor module of claim 1, wherein the SMD component is coupled to the land pads with solder bumps.

### Claim 6 (depends on 1)

The semiconductor module of claim 1, wherein the build-up interconnect structure comprises high-density multilayer routing layers.

### Claim 7 (depends on 1)

The semiconductor module of claim 1, wherein:
the SMD component is partially within a footprint of the semiconductor die and partially without a footprint of the semiconductor die; and
at least one of the SMD land pads is positioned over an edge of the footprint of the semiconductor die within the fully molded structure.

### Claim 8 (depends on 1)

The semiconductor module of claim 1, further comprising:
a first output connector of the module adapted to be coupled to a battery; and
a second connector of the module adapted to be coupled to a display.

### Claim 9 (depends on 1)

The semiconductor module of claim 1, wherein a second encapsulant material is disposed over and around the SMD component to form a fully molded top portion.

### Claim 10

A semiconductor module, comprising:
a fully molded base portion comprising a planar surface that further comprises:
a semiconductor die disposed within the fully molded base portion, the semiconductor die comprising contact pads,
conductive pillars coupled to the contact pads and extending to the planar surface, and
an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion;
a build-up interconnect structure comprising a routing layer disposed over the fully molded base portion;
at least one SMD component (SMD) electrically coupled to the routing layer, wherein the SMD component comprises one or more of a semiconductor die, a wafer level chip scale package (WLCSP), an integrated circuit (IC), a surface mount device, an active device, or a passive device or a solderable passive such as a resistor or a capacitor; and
a second encapsulant material disposed over and around the SMD component to form a fully molded top portion.

### Claim 11 (depends on 10)

The semiconductor module of claim 10, wherein the SMD component being electrically coupled to the routing layer further comprises:
the SMD component comprising solderable terminations;
solder paste disposed over the routing layer; and
the solderable terminations being disposed over, and electrically coupled to, the routing layer when the solderable terminations are in contact with the solder paste.

### Claim 12 (depends on 10)

The semiconductor module of claim 10, wherein the IC component is coupled to the routing layer with solder bumps.

### Claim 13 (depends on 10)

The semiconductor module of claim 10, wherein:
the SMD component is partially within a footprint of the semiconductor die and partially without a footprint of the semiconductor die.

### Claim 14 (depends on 10)

The semiconductor module of claim 10, further comprising a shielding layer disposed over the encapsulant material of the fully molded base portion and the second encapsulant material of the fully molded top portion, the shielding layer being coupled to build-up interconnect structure.

### Claim 15 (depends on 10)

The semiconductor module of claim 10, wherein the encapsulant material of the fully molded base portion is of a same material as the second encapsulant of the fully molded top portion.

### Claim 16

A method of making a semiconductor module, comprising:
forming electrical interconnects on a semiconductor die;
encapsulating the semiconductor die with an encapsulant to form a first embedded portion with the electrical interconnects exposed from the encapsulant;
forming a build-up interconnect structure comprising a conductive RDL layer over the first embedded portion after encapsulating the semiconductor die, the build-up interconnect structure being electrically connected to the electrical interconnects, a position or alignment of a portion of the build-up interconnect structure being adjusted by unit specific patterning;
forming surface mount device (SMD) land pads electrically coupled to the conductive RDL layer; and
coupling a SMD component to the SMD land pads with surface mount technology (SMT) to provide an electrical connection between the SMD component and the semiconductor die through the conductive pillars and the build-up interconnect structure.

### Claim 17 (depends on 16)

The method of claim 16 further comprising forming the build-up interconnect structure comprising the conductive RDL routing layer being adjusted by unit specific patterning to account for shift of the semiconductor die within the first embedded portion.

### Claim 18 (depends on 16)

The method of claim 16, wherein the SMD component comprises a semiconductor die, a wafer level chip scale package (WLCSP), an integrated circuit (IC), a surface mount device, an active device, or a passive device or a solderable passive such as a resistor or a capacitor.

### Claim 19 (depends on 16)

The method of claim 16, further comprising electrically testing the semiconductor die within the first embedded portion before coupling any of the SMD components to the first embedded portion.

### Claim 20 (depends on 16)

The method of claim 16, further comprising coupling the SMD component to the SMD land pads so that the SMD component is partially within a footprint of the semiconductor die and partially without a footprint of the semiconductor die.