# US 10,373,898 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 10,373,898 B2
- Document ID: US10373898B2
- Status: Granted
- Kind: B2
- Application number: 15/447,149
- Filed: 2017-03-02
- Published: 2018-01-04
- Granted: 2019-08-06
- Earliest claimed: 2016-06-29
- Assignees: Mitsubishi Electric Corporation
- Applicants: Mitsubishi Electric Corporation
- Inventors: Yuji Iwai; Katsumi Miyawaki
- Web page: https://patentgrep.com/patent/US10373898B2

## CPC

- H10W 90/811: {Multiple chips on leadframes}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/435: {of insulating layers on leadframes, e.g. bridging members}
- H10W 70/457: {of metallic layers on leadframes}
- H10W 70/465: {Bumps or wires}
- H10W 70/468: {Circuit boards}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/10: characterised by their shape or disposition
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a lead frame comprising a first terminal and a second terminal for grounding, a sealing resin which covers the lead frame, an exposed part which is a part of the second terminal and is exposed from the sealing resin and a conductive material which covers the surface of the sealing resin and contacts the second terminal at the exposed part.

## Claims

### Claim 1

A semiconductor device comprising:
a lead frame comprising at least one first terminal and at least one second terminal for grounding;
a sealing resin covering the lead frame and defining an end of the semiconductor device, the sealing resin comprising a thin wall part above the at least one first terminal, the thin wall part having a height equal to a height of the at least one second terminal at the end of the semiconductor device;
an exposed part which is a part of the at least one second terminal and is exposed from the sealing resin; and
a conductive material which covers the surface of the sealing resin and contacts the at least one second terminal at the exposed part, wherein
a first notch portion is provided in the at least one second terminal at the end of the semiconductor device, and a second notch portion is provided at the thin wall part and above the at least one first terminal, and
the conductive material contacts the at least one second terminal in the first notch portion.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
the at least one first terminal and the at least one second terminal are arranged at the end of the semiconductor device, and
the at least one second terminal is higher than the at least one first terminal at the end of the semiconductor device.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein
the at least one second terminal comprises:
a third terminal which is comprised by the lead frame and has the same height as the at least one first terminal; and
a conductive piece which is disposed on the surface of the third terminal.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2, wherein
the lead frame comprises a die pad for mounting a semiconductor chip, and
the at least one second terminal is electrically conducted with the die pad.

### Claim 5 (depends on 2)

The semiconductor device according to claim 2, wherein
the exposed part and the thin wall part are formed so as to enclose a semiconductor chip, and
the conductive material covers the surfaces of the exposed part and the thin wall part which enclose the semiconductor chip.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein
the first notch portion, the second notch portion and a third notch portion provided in a resin portion of the sealing resin between the first notch portion and the second notch portion form a peripheral notch that extends around the entire periphery of the semiconductor device in plan view.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein
the at least one first terminal includes a plurality of first terminals and the at least one second terminal includes a plurality of second terminals, and
the plurality of the first terminals and the plurality of the second terminals are arranged at the end of the semiconductor device alternately.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein
the first notch portion, the second notch portion and a third notch portion provided in a resin portion of the sealing resin between the first notch portion and the second notch portion form a peripheral notch that extends around the periphery of the semiconductor device in plan view.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein
the at least one first terminal includes a plurality of first terminals and the at least one second terminal includes a plurality of second terminals, and
the plurality of the first terminals and the plurality of the second terminals are arranged at the end of the semiconductor device alternately.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein
the first notch portion provides a thin part of the at least one second terminal, and
a height of the thin part of the at least one second terminal is higher than a height of the at least one first terminal.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein
a height of the at least one second terminal in the first notch portion is higher than a height of the at least one first terminal.