# US 10,373,895 B2 · Semiconductor device having die pads with exposed surfaces

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- Number: US 10,373,895 B2
- Document ID: US10373895B2
- Status: Granted
- Kind: B2
- Application number: 15/375,812
- Filed: 2016-12-12
- Published: 2018-06-14
- Granted: 2019-08-06
- Earliest claimed: 2016-12-12
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Edward Fuergut; Martin Gruber; Wolfgang Scholz; Ralf Otremba
- Web page: https://patentgrep.com/patent/US10373895B2

## CPC

- H10W 70/442: {of multiple leadframes in a single chip}
- H10W 40/037: {Assembling together parts thereof}
- H10W 70/041: {Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps}
- H10W 70/048: {Mechanical treatments, e.g. punching, cutting, deforming or cold welding}
- H10W 70/465: {Bumps or wires}
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 72/071: {Connecting or disconnecting}
- H10W 74/01: Manufacture or treatment
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/00: Package configurations
- H10W 90/811: {Multiple chips on leadframes}
- H10W 72/0198: {batch processes}
- H10W 72/07552: {changes in structures or sizes}
- H10W 72/527: {Multiple bond wires having different sizes}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 74/014: {using batch processing}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/20: Configurations of stacked chips
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/752: {between stacked chips}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first lead frame, a second lead frame, a first semiconductor chip, and an encapsulation material. The first lead frame includes a first die pad having a first surface and a second surface opposite to the first surface. The second lead frame includes a second die pad having a first surface and a second surface opposite to the first surface. The first surface of the second die pad faces the first surface of the first die pad. The first semiconductor chip is attached to the first surface of the first die pad. The encapsulation material encapsulates the first semiconductor chip and portions of the first lead frame and the second lead frame. The encapsulation material has a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad.

## Claims

### Claim 1

A semiconductor device comprising:
a first lead frame comprising a first die pad having a first surface and a second surface opposite to the first surface of the first die pad;
a second lead frame comprising a second die pad having a first surface and a second surface opposite to the first surface of the second die pad, the first surface of the second die pad facing the first surface of the first die pad, wherein the second die pad is directly electrically connected to the first die pad;
a first semiconductor chip attached to the first surface of the first die pad; and
an encapsulation material encapsulating the first semiconductor chip and portions of the first lead frame and the second lead frame, the encapsulation material having a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second semiconductor chip attached to the first surface of the second die pad.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first semiconductor chip is electrically coupled to the second semiconductor chip.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
bond wires electrically coupling the first semiconductor chip to leads of the first lead frame.

### Claim 5

A semiconductor device comprising:
a first lead frame comprising a first die pad having a first surface and a second surface opposite to the first surface of the first die pad;
a second lead frame comprising a second die pad having a first surface and a second surface opposite to the first surface of the second die pad, the first surface of the second die pad facing the first surface of the first die pad;
a first semiconductor chip attached to the first surface of the first die pad; and
an encapsulation material encapsulating the first semiconductor chip and portions of the first lead frame and the second lead frame, the encapsulation material having a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad, a hole through the encapsulation material extending from the first surface of the encapsulation material to the second surface of the encapsulation material.

### Claim 6

A semiconductor device comprising:
a first lead frame comprising a first die pad having a first surface and a second surface opposite to the first surface of the first die pad;
a second lead frame comprising a second die pad having a first surface and a second surface opposite to the first surface of the second die pad, the first surface of the second die pad facing the first surface of the first die pad;
a first semiconductor chip attached to the first surface of the first die pad; and
an encapsulation material encapsulating the first semiconductor chip and portions of the first lead frame and the second lead frame, the encapsulation material having a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad, wherein the semiconductor device is a through-hole device.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device is a surface mount device.

### Claim 8

A semiconductor device comprising:
a first lead frame comprising a first die pad having a first surface and a second surface opposite to the first surface of the first die pad;
a second lead frame comprising a second die pad having a first surface and a second surface opposite to the first surface of the second die pad, the first surface of the second die pad facing the first surface of the first die pad;
a first semiconductor chip attached to the first surface of the first die pad;
a second semiconductor chip attached to the first surface of the second die pad; and
an encapsulation material encapsulating the first semiconductor chip and the second semiconductor chip and portions of the first lead frame and the second lead frame, the encapsulation material having a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising:
a third semiconductor chip; and
a fourth semiconductor chip;
wherein the first lead frame comprises a third die pad having a first surface and a second surface opposite to the first surface of the third die pad;
wherein the second lead frame comprises a fourth die pad having a first surface and a second surface opposite to the first surface of the fourth die pad;
wherein the third semiconductor chip is attached to the first surface of the third die pad;
wherein the fourth semiconductor chip is attached to the first surface of the fourth die pad; and
wherein the encapsulation material encapsulates the third semiconductor chip and the fourth semiconductor chip and wherein the first surface of the encapsulation material is aligned with the second surface of the third die pad and the second surface of the encapsulation material is aligned with the second surface of the fourth die pad.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the first semiconductor chip comprises a power semiconductor chip; and
wherein the second semiconductor chip comprises a logic chip.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the first semiconductor chip comprises a power transistor chip; and
wherein the second semiconductor chip comprises a diode chip.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the first semiconductor chip comprises a first power transistor chip; and
wherein the second semiconductor chip comprises a second power transistor chip.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, further comprising:
an interconnect board between the first semiconductor chip and the second semiconductor chip electrically coupling the first semiconductor chip to the second semiconductor chip.

### Claim 14

A method to fabricate a semiconductor device, the method comprising:
attaching a first semiconductor chip to a first surface of a first die pad of a first lead frame, the first die pad having a second surface opposite to the first surface of the first die pad;
attaching a second semiconductor chip to a first surface of a second die pad of a second lead frame, the second die pad having a second surface opposite to the first surface of the second die pad;
stacking the second lead frame on the first lead frame such that the first surface of the first die pad faces the first surface of the second die pad; and
encapsulating the first semiconductor chip and the second semiconductor chip and portions of the first lead frame and the second lead frame with an encapsulation material such that the second surface of the first die pad is aligned with a first surface of the encapsulation material and the second surface of the second die pad is aligned with a second surface of the encapsulation material.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
electrically coupling the second lead frame to the first lead frame.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
cutting leads of the second lead frame after stacking the second lead frame on the first lead frame.

### Claim 17 (depends on 14)

The method of claim 14, further comprising:
wire bonding the first semiconductor chip to leads of the first lead frame; and
wire bonding the second semiconductor chip to leads of the second lead frame.

### Claim 18 (depends on 14)

The method of claim 14, further comprising:
electrically coupling the first semiconductor chip to the second semiconductor chip.

### Claim 19 (depends on 14)

The method of claim 14, further comprising:
attaching a first heat sink to the second surface of the first die pad and the first surface of the encapsulation material; and
attaching a second heat sink to the second surface of the second die pad and the second surface of the encapsulation material.

### Claim 20 (depends on 1)

The semiconductor device of claim 1, the first lead frame including a first lead extending directly from the first die pad, and the second lead frame being directly electrically connected to the first die pad by a lead portion extending from the second die pad and directly connecting to the first lead.