# US 10,373,885 B2 · 3D stacked-chip package

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,373,885 B2
- Document ID: US10373885B2
- Status: Granted
- Kind: B2
- Application number: 15/608,466
- Filed: 2017-05-30
- Published: 2017-09-14
- Granted: 2019-08-06
- Earliest claimed: 2014-04-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hua Yu; Ming-Fa Chen; Wen-Sen Lu; Wen-Chih Chiou; Wen-Ching Tsai
- Web page: https://patentgrep.com/patent/US10373885B2

## CPC

- H10W 74/129: {forming a chip-scale package [CSP]}
- H10P 50/283: {by chemical means}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates}
- H10W 20/0265: {characterised by the sidewall insulation}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/076: {in via holes or trenches}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2125: {Top-view shapes}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 40/10: Arrangements for heating
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/072: {of bump connectors}
- H10W 74/016: {using moulds}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/66: Conductive materials thereof
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/019: {of bond pads}
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 72/90: Bond pads, in general
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.

## Claims

### Claim 1

A method, comprising:
bonding a first die to a second die by directly bonding a first oxide layer of the first die to a second oxide layer of the second die with an oxide-to-oxide bond, the first die comprises a first semiconductor substrate and the second die comprises a second semiconductor substrate;
forming a first opening in the second die after the bonding the first die to the second die, wherein the first opening extends through the second semiconductor substrate and exposes a first conductive element of the first die or the second die;
forming a first via in the first opening, the first via is electrically insulated from the second semiconductor substrate by a first spacer;
mounting a third die over the second die, the third die having a third semiconductor substrate;
forming a second opening in the third die after the mounting the third die over the second die, the second opening extending through the third semiconductor substrate and exposing the first via; and
forming a second via in the second opening, the second via is electrically insulated from the third semiconductor substrate by a second spacer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a first molding compound over the first die and around the second die prior to the forming the first via; and
forming a second molding compound around the third die prior to the forming the second via.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first molding compound is disposed between the second die and the third die along a direction perpendicular to a major surface of the second semiconductor substrate.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
forming a third via extending through the first molding compound adjacent the second die prior to the mounting the third die, wherein the third via extends through the first molding compound and contacts a second conductive element of the first die.

### Claim 5 (depends on 4)

The method of claim 4, further comprising forming a fourth via through the second molding compound, wherein the fourth via contacts at least one of the first via or the third via.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
prior to forming the first via, depositing a spacer layer along sidewalls and a bottom surface of the first opening; and
etching the spacer layer to remove lateral portions of the spacer layer and define the first spacer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first conductive element is disposed in the first die, and wherein the first opening further exposes a third conductive element of the second die over the first conductive element.

### Claim 8 (depends on 1)

The method of claim 1, wherein the third conductive element acts as an etch stop layer during forming the first opening.

### Claim 9

A method comprising:
bonding first semiconductor die to a second semiconductor die using a direct oxide-to-oxide bond;
forming an insulating material over a first one of the first semiconductor die and the second semiconductor die, the insulating material at least laterally encapsulating a second one of the first semiconductor die and the second semiconductor die;
patterning a first opening extending through a first semiconductor substrate of the first semiconductor die;
forming a first spacer along a first sidewall of the first opening; and
forming a conductive via in the first opening, the first spacer electrically insulates the conductive via from the first semiconductor substrate.

### Claim 10 (depends on 9)

The method of claim 9, wherein the insulating material comprises a molding compound.

### Claim 11 (depends on 9)

The method of claim 9, wherein a width of the first one of the first semiconductor die and the second semiconductor die has a different width than the second one of the first semiconductor die and the second semiconductor die.

### Claim 12 (depends on 9)

The method of claim 9, further comprising planarizing the insulating material so that a lateral surface of the insulating material is substantially level with a lateral surface of the second one of the first semiconductor die and the second semiconductor die.

### Claim 13 (depends on 9)

The method of claim 9, wherein forming the insulating material further comprises forming the insulating material over the second one of the first semiconductor die and the second semiconductor die, and wherein patterning the first opening further comprises patterning the first opening through at least a portion of the insulating material.

### Claim 14 (depends on 9)

The method of claim 9, further comprising forming redistribution layers over the first semiconductor die and the second semiconductor die, wherein the redistribution layers are electrically connected to the conductive via.

### Claim 15 (depends on 9)

The method of claim 9, wherein patterning the first opening comprises exposing a first conductive feature in the second semiconductor die.

### Claim 16 (depends on 9)

The method of claim 9, wherein patterning the first opening further comprises exposing a second conductive feature in the first semiconductor die.

### Claim 17

A method comprising:
bonding first semiconductor die to a second semiconductor die, the first semiconductor die comprising a first semiconductor substrate, and the second semiconductor die comprising a second semiconductor substrate;
forming a first insulating material over the first semiconductor die and around the second semiconductor die;
patterning a first opening extending through the second semiconductor substrate and a portion of the first insulating material above the second semiconductor substrate;
forming a first spacer along a first sidewall of the first opening; and
forming a first conductive via in the first opening, the first spacer electrically insulates the first conductive via from the second semiconductor substrate.

### Claim 18 (depends on 17)

The method of claim 17, wherein a first portion of the first conductive via in the portion of the first insulating material above the second semiconductor substrate is wider than a second portion of the first conductive via in the second semiconductor substrate.

### Claim 19 (depends on 17)

The method of claim 17 further comprising:
disposing a third semiconductor die over the second semiconductor die, the third semiconductor die comprising a third semiconductor substrate;
encapsulating the third semiconductor die in a second insulating material disposed over the first insulating material;
patterning a second opening extending through at least a portion of the second insulating material; and
forming a second conductive via in the second opening, the second conductive via contacting the first conductive via.

### Claim 20 (depends on 19)

The method of claim 19, wherein the second conductive via is laterally spaced apart from the second semiconductor die, and wherein the first conductive via has a fan-out configuration extending laterally past a sidewall of the second semiconductor die.