# US 10,373,884 B2 · Fan-out semiconductor package for packaging semiconductor chip and capacitors

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,373,884 B2
- Document ID: US10373884B2
- Status: Granted
- Kind: B2
- Application number: 15/278,248
- Filed: 2016-09-28
- Published: 2017-10-05
- Granted: 2019-08-06
- Earliest claimed: 2016-03-31
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Han Kim; Mi Ja Han; Kang Heon Hur; Young Gwan Ko
- Web page: https://patentgrep.com/patent/US10373884B2

## CPC

- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/655: Fan-out layouts
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/00: Package configurations
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The fan-out semiconductor package includes: a semiconductor chip having an active surface having a connection pad disposed thereon and an inactive surface disposed to oppose the active surface; a first capacitor disposed adjacently to the semiconductor chip; an encapsulant at least partially encapsulating the first connection member and the semiconductor chip; a first connection member disposed on the encapsulant, the first capacitor, and the semiconductor chip, and a second capacitor disposed on the other surface of the first connection member opposing one surface of the first connection member on which the semiconductor chip is disposed, wherein the first connection member includes a redistribution layer electrically connected to the connection pad of the semiconductor chip, the first capacitor, and the second capacitor, and the first capacitor and the second capacitor are electrically connected to the connection pad through a common power wiring of the redistribution layer.

## Claims

### Claim 1

A fan-out semiconductor package comprising:
a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface;
a first capacitor disposed adjacently to the semiconductor chip;
an encapsulant at least partially encapsulating the inactive surface of the semiconductor chip and the first capacitor;
a first connection member disposed on the encapsulant, the first capacitor, and the active surface of the semiconductor chip, and
a second capacitor disposed on the other surface of the first connection member opposing one surface of the first connection member on which the semiconductor chip is disposed,
wherein the first connection member includes a redistribution layer electrically connected to one of the connection pads of the semiconductor chip, the first capacitor, and the second capacitor, and
the first capacitor and the second capacitor are electrically connected to the one of the connection pads of the semiconductor chip through a common power wiring of the redistribution layer.

### Claim 2 (depends on 1)

The fan-out semiconductor package of claim 1, wherein C1 is equal to C2, in which C1 and C2 are capacitances of the first and second capacitors, respectively.

### Claim 3 (depends on 1)

The fan-out semiconductor package of claim 1, wherein t1 is greater than t2, in which t1 and t2 are thicknesses of the first and second capacitors, respectively.

### Claim 4 (depends on 1)

The fan-out semiconductor package of claim 1, wherein L1 is equal to L2, in which L1 and L2 are equivalent series inductances (ESL) of the first and second capacitors, respectively.

### Claim 5 (depends on 1)

The fan-out semiconductor package of claim 1, wherein R1 is equal to R2, in which R1 and R2 are equivalent series resistances (ESR) of the first and second capacitors, respectively.

### Claim 6 (depends on 1)

The fan-out semiconductor package of claim 1, wherein the first and second capacitors are connected to each other in parallel.

### Claim 7 (depends on 1)

The fan-out semiconductor package of claim 1, further comprising a passivation layer disposed on the other surface of the first connection member opposing the one surface of the first connection member on which the semiconductor chip is disposed and having openings exposing at least a portion of a wiring of the redistribution layer,
wherein the second capacitor is disposed on a surface of the passivation layer.

### Claim 8 (depends on 7)

The fan-out semiconductor package of claim 7, further comprising connection terminals disposed in the openings of the passivation layer,
wherein the connection terminals are disposed to surround the second capacitor and are electrically connected to other connection pads of the connection pads of the semiconductor chip.

### Claim 9 (depends on 1)

The fan-out semiconductor package of claim 1, further comprising a second connection member having a through-hole disposed on the second connection member,
wherein the semiconductor chip and the first capacitor are disposed in the through-hole,
the encapsulant covers an upper surface of the second connection member, and extends continuously from the upper surface of the second connection member and the inactive surface of the semiconductor chip to directly contact with the first connection member by passing the through-hole,
the encapsulant directly covers upper and side surfaces of the first capacitor and side surfaces of the semiconductor chip connecting the active and inactive surfaces to each other, and
a lower surface of the first capacitor opposing the upper surface of the first capacitor is in contact with the first connection member, and a lower surface of the second connection member opposing the upper surface of the second connection member is in contact with the first connection member.

### Claim 10 (depends on 9)

The fan-out semiconductor package of claim 9, wherein the second connection member includes a first insulating layer, a first redistribution layer contacting the first connection member and embedded in the first insulating layer, and a second redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the first redistribution layer is embedded, and
the first and second redistribution layers are electrically connected to the connection pads.

### Claim 11 (depends on 10)

The fan-out semiconductor package of claim 10, wherein the second connection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer, and
the third redistribution layer is electrically connected to the connection pads.

### Claim 12 (depends on 10)

The fan-out semiconductor package of claim 10, wherein a distance between the redistribution layer of the first connection member and the first redistribution layer is greater than that between the redistribution layer of the first connection member and the connection pads.

### Claim 13 (depends on 10)

The fan-out semiconductor package of claim 10, wherein the first redistribution layer is thicker than the redistribution layer of the first connection member.

### Claim 14 (depends on 10)

The fan-out semiconductor package of claim 10, wherein a lower surface of the first redistribution layer is disposed on a level above lower surfaces of the connection pads.

### Claim 15 (depends on 11)

The fan-out semiconductor package of claim 11, wherein the second redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

### Claim 16 (depends on 9)

The fan-out semiconductor package of claim 9, wherein the second connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on both surfaces of the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer, and
the first to third redistribution layers are electrically connected to the connection pads.

### Claim 17 (depends on 16)

The fan-out semiconductor package of claim 16, wherein the second connection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer, and
the fourth redistribution layer is electrically connected to the connection pads.

### Claim 18 (depends on 16)

The fan-out semiconductor package of claim 16, wherein the first insulating layer is thicker than the second insulating layer.

### Claim 19 (depends on 16)

The fan-out semiconductor package of claim 16, wherein the third redistribution layer is thicker than the redistribution layer of the first connection member.

### Claim 20 (depends on 16)

The fan-out semiconductor package of claim 16, wherein the first redistribution layer is disposed on a level between the active surface and the inactive surface of the semiconductor chip.

### Claim 21 (depends on 16)

The fan-out semiconductor package of claim 16, wherein a lower surface of the third redistribution layer is disposed on a level below lower surfaces of the connection pads.

### Claim 22 (depends on 1)

The fan-out semiconductor package of claim 1, wherein the first connection member includes an insulating layer in direct contact with the first capacitor, and vias penetrating through the insulating layer and directly connected to the connection pads of the semiconductor chip and the first capacitor, respectively.

### Claim 23 (depends on 22)

The fan-out semiconductor package of claim 22, wherein two of the vias respectively connected to the first capacitor and the one of the connection pads of the semiconductor chip are directly connected to the common power wiring.

### Claim 24 (depends on 1)

The fan-out semiconductor package of claim 1, wherein in a stacking direction of the first connection member and the semiconductor chip, the common power wiring overlaps with the one of the connection pads of the semiconductor chip, at least a portion of the first capacitor, and at least a portion of the second capacitor.