# US 10,373,883 B2 · Semiconductor package device and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,373,883 B2 - Document ID: US10373883B2 - Status: Granted - Kind: B2 - Application number: 15/795,203 - Filed: 2017-10-26 - Published: 2019-05-02 - Granted: 2019-08-06 - Earliest claimed: 2017-10-26 - Assignees: Advanced Semiconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Yu-An Fang; Chi Sheng Tseng - Web page: https://patentgrep.com/patent/US10373883B2 ## CPC - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 76/60: Seals - H10F 77/50: Encapsulations or containers (for photovoltaic modules H10F19/80) - H10F 77/60: Arrangements for cooling, heating, ventilating or compensating for temperature fluctuations - H10F 77/93: {Interconnections} - H10H 20/8506: {Containers} - H10H 20/857: Interconnections, e.g. lead-frames, bond wires or solder balls - H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) - H10W 70/68: Shapes or dispositions thereof - H10W 76/12: characterised by their shape - H10W 76/15: Containers comprising an insulating or insulated base - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 90/00: Package configurations - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS ## Abstract A semiconductor package device comprises a substrate, an electronic component and a protection layer. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a first opening penetrating the substrate. The electronic component is disposed on the first surface of the substrate. The protection layer is disposed on the second surface of the substrate. The protection layer has a first portion adjacent to the first opening and a second portion disposed farther away from the first opening than is the first portion of the protection layer. The first portion of the protection layer has a surface facing away from the second surface of the substrate. The second portion of the protection layer has a surface facing away from the second surface of the substrate. A distance between the surface of the first portion of the protection layer and the second surface of the substrate is greater than a distance between the surface of the second portion of the protection layer and the second surface of the substrate. ## Claims ### Claim 1 A semiconductor package device, comprising: a substrate having a first surface and a second surface opposite to the first surface, the substrate defining a first opening penetrating the substrate; an electronic component disposed on the first surface of the substrate; a protection layer disposed on the second surface of the substrate, the protection layer comprising a first portion adjacent to the first opening and a second portion disposed farther away from the first opening than is the first portion of the protection layer, the first portion of the protection layer having a surface facing away from the second surface of the substrate, the second portion of the protection layer having a surface facing away from the second surface of the substrate, wherein a distance between the surface of the first portion of the protection layer and the second surface of the substrate is greater than a distance between the surface of the second portion of the protection layer and the second surface of the substrate. ### Claim 2 (depends on 1) The semiconductor package device of claim 1, further comprising a conductive pad disposed on the second surface of the substrate, wherein the protection layer further includes a third portion covering a portion of the conductive pad and having a surface facing away from the second surface of the substrate, and wherein the distance between the surface of the first portion of the protection layer and the second surface of the substrate is substantially equal to or greater than a distance between the surface of the third portion of the protection layer and the second surface of the substrate. ### Claim 3 (depends on 2) The semiconductor package device of claim 2, wherein the protection layer is conformal to the conductive pad. ### Claim 4 (depends on 1) The semiconductor package device of claim 1, further comprising a metal structure disposed on the second surface of the substrate and covered by the first portion of the protection layer. ### Claim 5 (depends on 4) The semiconductor package device of claim 4, wherein the metal structure comprises a dummy pad or a grounding pad. ### Claim 6 (depends on 4) The semiconductor package device of claim 4, wherein the metal structure surrounds the first opening. ### Claim 7 (depends on 1) The semiconductor package device of claim 1, further comprising a housing disposed on the first surface of the substrate and covering the electronic component. ### Claim 8 (depends on 1) The semiconductor package device of claim 1, wherein the protection layer includes a photosensitive material. ### Claim 9 (depends on 1) The semiconductor package device of claim 1, wherein the protection layer extends along the second surface of the substrate and protrudes beyond an edge of the first opening to define a second opening. ### Claim 10 (depends on 9) The semiconductor package device of claim 9, wherein a width of the first opening is greater than a width of the second opening. ### Claim 11 (depends on 1) The semiconductor package device of claim 1, further comprising a carrier disposed between the substrate and the electronic component, wherein the carrier defines a vent hole substantially aligned with the first opening of the substrate. ### Claim 12 (depends on 11) The semiconductor package device of claim 11, further comprising a sealing element surrounding the first opening and the vent hole. ### Claim 13 A semiconductor package device, comprising a substrate having a first surface and a second surface opposite to the first surface, the substrate defining a first opening penetrating the substrate; an electronic component disposed on the first surface of the substrate; a metal structure disposed on the second surface of the substrate and adjacent to the first opening; and a protection layer comprising a first portion covering the second surface of the substrate and a second portion covering the metal structure. ### Claim 14 (depends on 13) The semiconductor package device of claim 13, wherein a thickness of the first portion of the protection layer is substantially the same as a thickness of the second portion of the protection layer. ### Claim 15 (depends on 13) The semiconductor package device of claim 13, wherein a distance between a surface of the second portion of the protection layer and the second surface of the substrate is greater than a distance between a surface of the first portion of the protection layer and the second surface of the substrate. ### Claim 16 (depends on 13) The semiconductor package device of claim 13, further comprising a conductive pad disposed on the second surface of the substrate and farther away from the first opening than is the metal structure, the conductive pad spaced apart from the metal structure, wherein the protection layer comprises a third portion covering a portion of the conductive pad. ### Claim 17 (depends on 16) The semiconductor package device of claim 16, wherein the protection layer is conformal to the metal structure and the conductive pad. ### Claim 18 (depends on 13) The semiconductor package device of claim 13, wherein the metal structure surrounds the first opening. ### Claim 19 (depends on 13) The semiconductor package device of claim 13, wherein the metal structure comprises a dummy pad or a grounding pad. ### Claim 20 (depends on 13) The semiconductor package device of claim 13, further comprising a housing disposed on the first surface of the substrate and covering the electronic component. ### Claim 21 (depends on 13) The semiconductor package device of claim 13, wherein the protection layer includes a photosensitive material. ### Claim 22 (depends on 13) The semiconductor package device of claim 13, wherein the protection layer extends along the second surface of the substrate and protrudes beyond an edge of the first opening to define a second opening. ### Claim 23 (depends on 22) The semiconductor package device of claim 22, wherein the first opening is formed by mechanical drilling and the second opening is formed by a photographic technique. ### Claim 24 (depends on 13) The semiconductor package device of claim 13, further comprising a carrier disposed between the substrate and the electronic component, wherein the carrier defines a vent hole substantially aligned with the first opening of the substrate. ### Claim 25 (depends on 24) The semiconductor package device of claim 24, further comprising a sealing element surrounding the first opening and the vent hole. ### Claim 26 A semiconductor package device, comprising a substrate having a first surface and a second surface opposite to the first surface, the substrate defining a first opening penetrating the substrate; an electronic component disposed on the first surface of the substrate; a metal structure disposed on the second surface of the substrate; and a protection layer covering the metal structure and extending along the second surface of the substrate to define a second opening under the first opening. ### Claim 27 (depends on 26) The semiconductor package device of claim 26, wherein the first opening is formed by mechanical drilling and the second opening is formed by a photographic technique. ### Claim 28 (depends on 26) The semiconductor package device of claim 26, wherein a width of the first opening is greater than a width of the second opening. ### Claim 29 (depends on 26) The semiconductor package device of claim 26, wherein the protection layer includes a photosensitive material.